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Mon, 24 Jan 2022 17:21:24 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2AECAC605A; Mon, 24 Jan 2022 17:21:24 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8DEFEC6061; Mon, 24 Jan 2022 17:21:23 +0000 (GMT) Received: from localhost (unknown [9.163.24.67]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTPS; Mon, 24 Jan 2022 17:21:23 +0000 (GMT) From: Fabiano Rosas To: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] KVM: PPC: Book3S HV: HFSCR[PREFIX] does not exist In-Reply-To: <20220122105639.3477407-1-npiggin@gmail.com> References: <20220122105639.3477407-1-npiggin@gmail.com> Date: Mon, 24 Jan 2022 14:21:21 -0300 Message-ID: <87v8y9dp7y.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: FXI7684O8ER766dIWJrDntdySrmSDzJo X-Proofpoint-ORIG-GUID: 6Ttfrz_k7hH_G4c0AIG-a_NApHPlfa12 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-24_08,2022-01-24_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 impostorscore=0 adultscore=0 bulkscore=0 malwarescore=0 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201240114 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Nicholas Piggin writes: > This facility is controlled by FSCR only. Reserved bits should not be > set in the HFSCR register (although it's likely harmless as this > position would not be re-used, and the L0 is forgiving here too). > > Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas > --- > arch/powerpc/include/asm/reg.h | 1 - > arch/powerpc/kvm/book3s_hv.c | 2 +- > 2 files changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h > index 2835f6363228..1e14324c5190 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -417,7 +417,6 @@ > #define FSCR_DSCR __MASK(FSCR_DSCR_LG) > #define FSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */ > #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ > -#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG) > #define HFSCR_MSGP __MASK(FSCR_MSGP_LG) > #define HFSCR_TAR __MASK(FSCR_TAR_LG) > #define HFSCR_EBB __MASK(FSCR_EBB_LG) > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 84c89f08ae9a..be8914c3dde9 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -2830,7 +2830,7 @@ static int kvmppc_core_vcpu_create_hv(struct kvm_vcpu *vcpu) > * to trap and then we emulate them. > */ > vcpu->arch.hfscr = HFSCR_TAR | HFSCR_EBB | HFSCR_PM | HFSCR_BHRB | > - HFSCR_DSCR | HFSCR_VECVSX | HFSCR_FP | HFSCR_PREFIX; > + HFSCR_DSCR | HFSCR_VECVSX | HFSCR_FP; > if (cpu_has_feature(CPU_FTR_HVMODE)) { > vcpu->arch.hfscr &= mfspr(SPRN_HFSCR); > #ifdef CONFIG_PPC_TRANSACTIONAL_MEM