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Mon, 11 Oct 2021 18:44:44 +0000 (GMT) From: Fabiano Rosas To: Nicholas Piggin , kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH v3 02/52] powerpc/64s: guard optional TIDR SPR with CPU ftr test In-Reply-To: <20211004160049.1338837-3-npiggin@gmail.com> References: <20211004160049.1338837-1-npiggin@gmail.com> <20211004160049.1338837-3-npiggin@gmail.com> Date: Mon, 11 Oct 2021 15:44:41 -0300 Message-ID: <87v9235rl2.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: hR5DhmJGE9FcVR6Ei6iO0cGi7LzH_8BT X-Proofpoint-ORIG-GUID: R5CtTMJHCA2YQh6S1Myw23hnudgo1f_Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-11_06,2021-10-11_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110110107 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Nicholas Piggin writes: > The TIDR SPR only exists on POWER9. Avoid accessing it when the > feature bit for it is not set. Not related to this patch, but how does this work with compat mode? A P9 compat mode guest would get an invalid instruction when trying to access this SPR? > Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas > --- > arch/powerpc/kvm/book3s_hv.c | 12 ++++++++---- > arch/powerpc/xmon/xmon.c | 10 ++++++++-- > 2 files changed, 16 insertions(+), 6 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 2acb1c96cfaf..f4a779fffd18 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -3767,7 +3767,8 @@ static void load_spr_state(struct kvm_vcpu *vcpu) > mtspr(SPRN_EBBHR, vcpu->arch.ebbhr); > mtspr(SPRN_EBBRR, vcpu->arch.ebbrr); > mtspr(SPRN_BESCR, vcpu->arch.bescr); > - mtspr(SPRN_TIDR, vcpu->arch.tid); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) > + mtspr(SPRN_TIDR, vcpu->arch.tid); > mtspr(SPRN_AMR, vcpu->arch.amr); > mtspr(SPRN_UAMOR, vcpu->arch.uamor); > > @@ -3793,7 +3794,8 @@ static void store_spr_state(struct kvm_vcpu *vcpu) > vcpu->arch.ebbhr = mfspr(SPRN_EBBHR); > vcpu->arch.ebbrr = mfspr(SPRN_EBBRR); > vcpu->arch.bescr = mfspr(SPRN_BESCR); > - vcpu->arch.tid = mfspr(SPRN_TIDR); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) > + vcpu->arch.tid = mfspr(SPRN_TIDR); > vcpu->arch.amr = mfspr(SPRN_AMR); > vcpu->arch.uamor = mfspr(SPRN_UAMOR); > vcpu->arch.dscr = mfspr(SPRN_DSCR); > @@ -3813,7 +3815,8 @@ struct p9_host_os_sprs { > static void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs) > { > host_os_sprs->dscr = mfspr(SPRN_DSCR); > - host_os_sprs->tidr = mfspr(SPRN_TIDR); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) > + host_os_sprs->tidr = mfspr(SPRN_TIDR); > host_os_sprs->iamr = mfspr(SPRN_IAMR); > host_os_sprs->amr = mfspr(SPRN_AMR); > host_os_sprs->fscr = mfspr(SPRN_FSCR); > @@ -3827,7 +3830,8 @@ static void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu, > mtspr(SPRN_UAMOR, 0); > > mtspr(SPRN_DSCR, host_os_sprs->dscr); > - mtspr(SPRN_TIDR, host_os_sprs->tidr); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) > + mtspr(SPRN_TIDR, host_os_sprs->tidr); > mtspr(SPRN_IAMR, host_os_sprs->iamr); > > if (host_os_sprs->amr != vcpu->arch.amr) > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c > index dd8241c009e5..7958e5aae844 100644 > --- a/arch/powerpc/xmon/xmon.c > +++ b/arch/powerpc/xmon/xmon.c > @@ -2107,8 +2107,14 @@ static void dump_300_sprs(void) > if (!cpu_has_feature(CPU_FTR_ARCH_300)) > return; > > - printf("pidr = %.16lx tidr = %.16lx\n", > - mfspr(SPRN_PID), mfspr(SPRN_TIDR)); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) { > + printf("pidr = %.16lx tidr = %.16lx\n", > + mfspr(SPRN_PID), mfspr(SPRN_TIDR)); > + } else { > + printf("pidr = %.16lx\n", > + mfspr(SPRN_PID)); > + } > + > printf("psscr = %.16lx\n", > hv ? mfspr(SPRN_PSSCR) : mfspr(SPRN_PSSCR_PR));