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[2001:44b8:1113:6700:a084:b324:40b3:453d]) by smtp.gmail.com with ESMTPSA id o17sm1596866pjq.1.2019.12.18.00.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 00:23:14 -0800 (PST) From: Daniel Axtens To: Jordan Niethe , linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 03/18] powerpc: Add PREFIXED SRR1 bit for future ISA version In-Reply-To: <20191126052141.28009-4-jniethe5@gmail.com> References: <20191126052141.28009-1-jniethe5@gmail.com> <20191126052141.28009-4-jniethe5@gmail.com> Date: Wed, 18 Dec 2019 19:23:11 +1100 Message-ID: <87v9qet53k.fsf@dja-thinkpad.axtens.net> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au, Jordan Niethe Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Jordan Niethe writes: > Add the bit definition for exceptions caused by prefixed instructions. > > Signed-off-by: Jordan Niethe > --- > arch/powerpc/include/asm/reg.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h > index 6f9fcc3d4c82..0a6d39fb4769 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -778,6 +778,7 @@ > > #define SRR1_MCE_MCP 0x00080000 /* Machine check signal caused interrupt */ > #define SRR1_BOUNDARY 0x10000000 /* Prefixed instruction crosses 64-byte boundary */ > +#define SRR1_PREFIXED 0x20000000 /* Exception caused by prefixed instruction */ You could probably squash this with the previous patch, and maybe the next patch too. Regards, Daniel > > #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ > #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ > -- > 2.20.1