From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C6BBC4332F for ; Fri, 15 Dec 2023 05:02:30 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=uFmXIMrX; dkim-atps=neutral Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4Srxsw4MwFz3dLg for ; Fri, 15 Dec 2023 16:02:28 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=uFmXIMrX; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kernel.org (client-ip=2604:1380:40e1:4800::1; helo=sin.source.kernel.org; envelope-from=aneesh.kumar@kernel.org; receiver=lists.ozlabs.org) Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Srxry4lwMz3cXy for ; Fri, 15 Dec 2023 16:01:38 +1100 (AEDT) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 342C6CE25B7; Fri, 15 Dec 2023 05:01:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D7AAC433C8; Fri, 15 Dec 2023 05:01:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702616495; bh=8RH/h1jakl0y7fPQ+kWUq85u6w9KslnUix/YJd0gqak=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=uFmXIMrXVkH0fn/PsKKyhCuvCCKR72ILItsqoCmKdvQicjHJTk+itW07h9q+uxgTx 4S5Xy9zdMEROVAJXk2UlqHVCvs6I5971BZncNlgXD1hKoPgutrEHHlds3gysgQDnrX Ck3Z3aTsBWHh+UutJIO8B+GRu5Mn3FprvP/T20ycwjRfUjtOtmDguHYNFZIqK+7G9c 61CedmmpQ9Do9oyZ2KJa2OG2XfyFt0vydvqaKpbMQs0oCFPDRXJ+CkS1Cl0T57D0/N R1XkIMdk+2ODC2zza+9UphvjUoBwYb1TzVDIQ2ksM2kYQDZkEfUZ8Nu/pPblV1piWq 7RLuZxlrNt0dg== X-Mailer: emacs 29.1 (via feedmail 11-beta-1 I) From: Aneesh Kumar K.V To: Srikar Dronamraju , Michael Ellerman , Nicholas Piggin , Christophe Leroy Subject: Re: [PATCH v5 1/5] powerpc/smp: Enable Asym packing for cores on shared processor In-Reply-To: <20231214180720.310852-2-srikar@linux.vnet.ibm.com> References: <20231214180720.310852-1-srikar@linux.vnet.ibm.com> <20231214180720.310852-2-srikar@linux.vnet.ibm.com> Date: Fri, 15 Dec 2023 10:31:26 +0530 Message-ID: <87zfyct5y1.fsf@kernel.org> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Valentin Schneider , Vincent Guittot , Srikar Dronamraju , "Paul E. McKenney" , Peter Zijlstra , "ndesaulniers@google.com" , linux-kernel@vger.kernel.org, Rohan McLure , linuxppc-dev , Josh Poimboeuf Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Srikar Dronamraju writes: > If there are shared processor LPARs, underlying Hypervisor can have more > virtual cores to handle than actual physical cores. > > Starting with Power 9, a big core (aka SMT8 core) has 2 nearly > independent thread groups. On a shared processors LPARs, it helps to > pack threads to lesser number of cores so that the overall system > performance and utilization improves. PowerVM schedules at a big core > level. Hence packing to fewer cores helps. > .... > +/* > + * On shared processor LPARs scheduled on a big core (which has two or more > + * independent thread groups per core), prefer lower numbered CPUs, so > + * that workload consolidates to lesser number of cores. > + */ > +static __ro_after_init DEFINE_STATIC_KEY_FALSE(splpar_asym_pack); DEFINE_STATIC_KEY_FALSE_RO ? > + > /* > * P9 has a slightly odd architecture where pairs of cores share an L2 cache. > * This topology makes it *much* cheaper to migrate tasks between adjacent cores > @@ -1011,9 +1018,20 @@ static int powerpc_smt_flags(void) > */ -aneesh