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Wed, 13 Oct 2021 16:51:59 +0000 (GMT) Received: from localhost (unknown [9.211.73.118]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTPS; Wed, 13 Oct 2021 16:51:59 +0000 (GMT) From: Fabiano Rosas To: Michael Ellerman , Nicholas Piggin , kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH v3 02/52] powerpc/64s: guard optional TIDR SPR with CPU ftr test In-Reply-To: <87k0ijm1ty.fsf@mpe.ellerman.id.au> References: <20211004160049.1338837-1-npiggin@gmail.com> <20211004160049.1338837-3-npiggin@gmail.com> <87v9235rl2.fsf@linux.ibm.com> <87k0ijm1ty.fsf@mpe.ellerman.id.au> Date: Wed, 13 Oct 2021 13:51:57 -0300 Message-ID: <87zgrckguq.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: nVEXXV6283GjZCd5cWN6RoZ7IhhktV8H X-Proofpoint-ORIG-GUID: ziC5t9dymdhUy6p_aRc2LKu1e9Zx0vJS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-13_06,2021-10-13_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 spamscore=0 suspectscore=0 mlxscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1011 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110130104 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Michael Ellerman writes: > Fabiano Rosas writes: >> Nicholas Piggin writes: >> >>> The TIDR SPR only exists on POWER9. Avoid accessing it when the >>> feature bit for it is not set. >> >> Not related to this patch, but how does this work with compat mode? A P9 >> compat mode guest would get an invalid instruction when trying to access >> this SPR? > > Good question. > > I assume you're talking about P9 compat mode on P10. > > In general compat mode only applies to userspace, because it's > implemented by setting the PCR which only (mostly?) applies to PR=3D1. > > I don't think there's any special casing in the ISA for the TIDR, so I > think it just falls into the unimplemented SPR case for mt/fspr. > > That's documented in Book III section 5.4.4, in particular on page 1171 > it says: > > Execution of this instruction specifying an SPR number > that is undefined for the implementation causes one of > the following. > =E2=80=A2 if spr[0]=3D0: > - if MSR[PR]=3D1: Hypervisor Emulation Assistance interrupt > - if MSR[PR]=3D0: Hypervisor Emulation Assistance interrupt for SPR > 0,4,5, and 6, and no operation (i.e., the instruction is treated > as a no-op) when LPCR[EVIRT]=3D0 and Hypervisor Emulation Assistance > interrupt when LPCR[EVIRT]=3D1 for all other SPRs I knew this must have been somewhere in there but had no idea how to find it. Thanks. > Linux doesn't set EVIRT, and I assume neither does phyp, so it behaves > like a nop. > > We actually use that behaviour in xmon to detect that an SPR is not > implemented, by noticing that the mfspr has no effect on the target > register, see dump_one_spr(). > > We should really write some docs on compat mode in the linuxppc wiki > and/or Documentation ;) Hmm I was not aware we had a wiki. I'll see if I can contribute something. I need to go learn all this stuff first, though =3DD. > > cheers