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Mon, 19 Sep 2022 06:03:46 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D9C1DA4053; Mon, 19 Sep 2022 06:03:20 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2E5D7A4040; Mon, 19 Sep 2022 06:03:19 +0000 (GMT) Received: from [9.43.125.247] (unknown [9.43.125.247]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Sep 2022 06:03:18 +0000 (GMT) Content-Type: multipart/alternative; boundary="------------xnH1tx2oswo1w1EnfCqTvUwT" Message-ID: <895f4387-582a-6d60-a176-e2112f506e12@linux.ibm.com> Date: Mon, 19 Sep 2022 11:33:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PACTH v2] powerpc/pseries/mce: Avoid instrumentation in realmode Content-Language: en-US To: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au References: <20220905063811.16454-1-ganeshgr@linux.ibm.com> From: Ganesh In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: AceP4uWgcU3JhxDaC-TzwUxKYIIHO99E X-Proofpoint-ORIG-GUID: u5za0AjZP54b_r_2w-7Rj-DUW-k82WTI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-19_03,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 mlxlogscore=772 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209190039 X-Mailman-Approved-At: Mon, 19 Sep 2022 18:12:32 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mahesh@linux.ibm.com, sachinp@linux.ibm.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" This is a multi-part message in MIME format. --------------xnH1tx2oswo1w1EnfCqTvUwT Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/7/22 09:49, Nicholas Piggin wrote: > On Mon Sep 5, 2022 at 4:38 PM AEST, Ganesh Goudar wrote: >> Part of machine check error handling is done in realmode, >> As of now instrumentation is not possible for any code that >> runs in realmode. >> When MCE is injected on KASAN enabled kernel, crash is >> observed, Hence force inline or mark no instrumentation >> for functions which can run in realmode, to avoid KASAN >> instrumentation. >> >> Signed-off-by: Ganesh Goudar >> --- >> v2: Force inline few more functions. >> --- >> arch/powerpc/include/asm/hw_irq.h | 8 ++++---- >> arch/powerpc/include/asm/interrupt.h | 2 +- >> arch/powerpc/include/asm/rtas.h | 4 ++-- >> arch/powerpc/kernel/rtas.c | 4 ++-- >> 4 files changed, 9 insertions(+), 9 deletions(-) >> >> diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h >> index 26ede09c521d..3264991fe524 100644 >> --- a/arch/powerpc/include/asm/hw_irq.h >> +++ b/arch/powerpc/include/asm/hw_irq.h >> @@ -111,7 +111,7 @@ static inline void __hard_RI_enable(void) >> #ifdef CONFIG_PPC64 >> #include >> >> -static inline notrace unsigned long irq_soft_mask_return(void) >> +static __always_inline notrace unsigned long irq_soft_mask_return(void) >> { >> return READ_ONCE(local_paca->irq_soft_mask); >> } >> @@ -121,7 +121,7 @@ static inline notrace unsigned long irq_soft_mask_return(void) >> * for the critical section and as a clobber because >> * we changed paca->irq_soft_mask >> */ >> -static inline notrace void irq_soft_mask_set(unsigned long mask) >> +static __always_inline notrace void irq_soft_mask_set(unsigned long mask) >> { >> /* >> * The irq mask must always include the STD bit if any are set. > This doesn't give a reason why it's __always_inline, and having the > notrace attribute makes it possibly confusing. I think it would be easy > for someone to break without realising. Could you add a noinstr to these > instead / as well? Yeah we can add noinstr. Missed to see your comment, Sorry for the delayed reply > > What about adding a 'realmode' function annotation that includes noinstr? You mean to define a new function annotation? --------------xnH1tx2oswo1w1EnfCqTvUwT Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit
On 9/7/22 09:49, Nicholas Piggin wrote:
On Mon Sep 5, 2022 at 4:38 PM AEST, Ganesh Goudar wrote:
Part of machine check error handling is done in realmode,
As of now instrumentation is not possible for any code that
runs in realmode.
When MCE is injected on KASAN enabled kernel, crash is
observed, Hence force inline or mark no instrumentation
for functions which can run in realmode, to avoid KASAN
instrumentation.

Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com>
---
v2: Force inline few more functions.
---
 arch/powerpc/include/asm/hw_irq.h    | 8 ++++----
 arch/powerpc/include/asm/interrupt.h | 2 +-
 arch/powerpc/include/asm/rtas.h      | 4 ++--
 arch/powerpc/kernel/rtas.c           | 4 ++--
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 26ede09c521d..3264991fe524 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -111,7 +111,7 @@ static inline void __hard_RI_enable(void)
 #ifdef CONFIG_PPC64
 #include <asm/paca.h>
 
-static inline notrace unsigned long irq_soft_mask_return(void)
+static __always_inline notrace unsigned long irq_soft_mask_return(void)
 {
 	return READ_ONCE(local_paca->irq_soft_mask);
 }
@@ -121,7 +121,7 @@ static inline notrace unsigned long irq_soft_mask_return(void)
  * for the critical section and as a clobber because
  * we changed paca->irq_soft_mask
  */
-static inline notrace void irq_soft_mask_set(unsigned long mask)
+static __always_inline notrace void irq_soft_mask_set(unsigned long mask)
 {
 	/*
 	 * The irq mask must always include the STD bit if any are set.
This doesn't give a reason why it's __always_inline, and having the
notrace attribute makes it possibly confusing. I think it would be easy
for someone to break without realising. Could you add a noinstr to these
instead / as well?
Yeah we can add noinstr. Missed to see your comment, Sorry for the delayed reply

What about adding a 'realmode' function annotation that includes noinstr?
You mean to define a new function annotation?

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