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Subject: Re: [PATCH][v2] powerpc/fsl-pci: use 'Header Type' to identify PCIE
 mode
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From: Kumar Gala <galak@kernel.crashing.org>
In-Reply-To: <1348465852-6507-1-git-send-email-Minghuan.Lian@freescale.com>
Date: Thu, 27 Sep 2012 07:33:08 -0500
Message-Id: <8BCDA75C-2454-4301-B40F-86E5AC023FD3@kernel.crashing.org>
References: <1348465852-6507-1-git-send-email-Minghuan.Lian@freescale.com>
To: Minghuan Lian <Minghuan.Lian@freescale.com>
Cc: linuxppc-dev@lists.ozlabs.org
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On Sep 24, 2012, at 12:50 AM, Minghuan Lian wrote:

> The original code uses 'Programming Interface' field to judge if PCIE =
is
> EP or RC mode, however, some latest silicons do not support this =
functionality.
> According to PCIE specification, 'Header Type' offset 0x0e is used to
> indicate header type, so change code to use 'Header Type' field to
> judge PCIE mode. Because FSL PCI controller does not support 'Header =
Type',
> patch still uses 'Programming Interface' to identify PCI mode.
>=20
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> Change log:
> v2 -=20
> keep the original PCI initialization order according to kumar's =
recommendations.
>=20
> arch/powerpc/sysdev/fsl_pci.c |   37 =
++++++++++++++++++++++++-------------
> 1 file changed, 24 insertions(+), 13 deletions(-)

applied to next

- k=