From: Russell Currey <ruscur@russell.cc>
To: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: linuxppc-dev@lists.ozlabs.org, benh@kernel.crashing.org,
alistair@popple.id.au, tpearson@raptorengineering.com
Subject: Re: [PATCH 1/3] powerpc/powernv/pci: Track largest available TCE order per PHB
Date: Tue, 03 Jul 2018 15:49:47 +1000 [thread overview]
Message-ID: <8e6ab216ef609df96087d01e9e0dd69906e6e9ee.camel@russell.cc> (raw)
In-Reply-To: <20180702173426.1254ecd0@aik.ozlabs.ibm.com>
On Mon, 2018-07-02 at 17:34 +1000, Alexey Kardashevskiy wrote:
> On Mon, 2 Jul 2018 17:32:56 +1000
> Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
>
> > On Fri, 29 Jun 2018 17:34:35 +1000
> > Russell Currey <ruscur@russell.cc> wrote:
> >
> > > Knowing the largest possible TCE size of a PHB is useful, so get
> > > it
> > > out of the device tree. This relies on the property being added
> > > in
> > > OPAL.
> > >
> > > It is assumed that any PHB4 or later machine would be running
> > > firmware that implemented this property, and otherwise assumed to
> > > be PHB3, which has a maximum TCE order of 28 bits or 256MB TCEs.
> > >
> > > This is used later in the series.
> > >
> > > Signed-off-by: Russell Currey <ruscur@russell.cc>
> > > ---
> > > arch/powerpc/platforms/powernv/pci-ioda.c | 16 ++++++++++++++++
> > > arch/powerpc/platforms/powernv/pci.h | 3 +++
> > > 2 files changed, 19 insertions(+)
> > >
> > > diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
> > > b/arch/powerpc/platforms/powernv/pci-ioda.c index
> > > 5bd0eb6681bc..17c590087279 100644 ---
> > > a/arch/powerpc/platforms/powernv/pci-ioda.c +++
> > > b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -3873,11 +3873,13
> > > @@
> > > static void __init pnv_pci_init_ioda_phb(struct device_node *np,
> > > struct resource r; const __be64 *prop64;
> > > const __be32 *prop32;
> > > + struct property *prop;
> > > int len;
> > > unsigned int segno;
> > > u64 phb_id;
> > > void *aux;
> > > long rc;
> > > + u32 val;
> > >
> > > if (!of_device_is_available(np))
> > > return;
> > > @@ -4016,6 +4018,20 @@ static void __init
> > > pnv_pci_init_ioda_phb(struct device_node *np, }
> > > phb->ioda.pe_array = aux + pemap_off;
> > >
> > > + phb->ioda.max_tce_order = 0;
> > > + /* Get TCE order from the DT. If it's not present,
> > > assume
> > > P8 */
> > > + if (!of_get_property(np, "ibm,supported-tce-sizes",
> > > NULL))
> > > {
> > > + phb->ioda.max_tce_order = 28; /* assume P8 256mb
> > > TCEs */
> > > + } else {
> > > + of_property_for_each_u32(np,
> > > "ibm,supported-tce-sizes", prop,
> > > + prop32, val) {
> > > + if (val > phb->ioda.max_tce_order)
> > > + phb->ioda.max_tce_order = val;
> > > + }
> > > + pr_debug("PHB%llx Found max TCE order of %d
> > > bits\n",
> > > + phb->opal_id, phb->ioda.max_tce_order);
> > > + }
> >
> >
> > pnv_ioda_parse_tce_sizes() does this, use it. It even reports 256MB
> > pages for P8 as in v4.18-rc3.
>
>
> ah, not, not in rc3, my bad. I'll post it soon.
Sure, whatever works, no need for duplication
>
>
> --
> Alexey
next prev parent reply other threads:[~2018-07-03 5:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-29 7:34 [PATCH 0/3] PCI DMA pseudo-bypass for powernv Russell Currey
2018-06-29 7:34 ` [PATCH 1/3] powerpc/powernv/pci: Track largest available TCE order per PHB Russell Currey
2018-07-02 7:32 ` Alexey Kardashevskiy
2018-07-02 7:34 ` Alexey Kardashevskiy
2018-07-03 5:49 ` Russell Currey [this message]
2018-06-29 7:34 ` [PATCH 2/3] powerpc/powernv: DMA operations for discontiguous allocation Russell Currey
2018-06-30 2:52 ` Benjamin Herrenschmidt
2018-07-02 8:47 ` Alexey Kardashevskiy
2018-07-03 6:09 ` Russell Currey
2018-07-04 6:12 ` Russell Currey
2018-06-29 7:34 ` [PATCH 3/3] powerpc/powernv/pci: Track TCE tables in debugfs Russell Currey
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