From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-x241.google.com (mail-io0-x241.google.com [IPv6:2607:f8b0:4001:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xW9hK2t29zDr39 for ; Mon, 14 Aug 2017 19:45:19 +1000 (AEST) Received: by mail-io0-x241.google.com with SMTP id m88so7206980iod.1 for ; Mon, 14 Aug 2017 02:45:18 -0700 (PDT) Subject: Re: [RFC PATCH v5 0/5] vfio-pci: Add support for mmapping MSI-X table To: linuxppc-dev@lists.ozlabs.org Cc: David Gibson , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org, Yongji Xie , Eric Auger , Kyle Mahlkuch , Alex Williamson , Jike Song , Bjorn Helgaas , Robin Murphy , Joerg Roedel , Arvind Yadav , Benjamin Herrenschmidt , David Woodhouse , Kirti Wankhede , Mauricio Faria de Oliveira , Neo Jia , Paul Mackerras , Vlad Tsyrklevich , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org References: <20170807072548.3023-1-aik@ozlabs.ru> From: Alexey Kardashevskiy Message-ID: <8f5f7b82-3c10-7f39-b587-db4c4424f04c@ozlabs.ru> Date: Mon, 14 Aug 2017 19:45:05 +1000 MIME-Version: 1.0 In-Reply-To: <20170807072548.3023-1-aik@ozlabs.ru> Content-Type: text/plain; charset=utf-8 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Folks, Is there anything to change besides those compiler errors and David's comment in 5/5? Or the while patchset is too bad? Thanks. On 07/08/17 17:25, Alexey Kardashevskiy wrote: > This is a followup for "[PATCH kernel v4 0/6] vfio-pci: Add support for mmapping MSI-X table" > http://www.spinics.net/lists/kvm/msg152232.html > > This time it is using "caps" in IOMMU groups. The main question is if PCI > bus flags or IOMMU domains are still better (and which one). > > > > Here is some background: > > Current vfio-pci implementation disallows to mmap the page > containing MSI-X table in case that users can write directly > to MSI-X table and generate an incorrect MSIs. > > However, this will cause some performance issue when there > are some critical device registers in the same page as the > MSI-X table. We have to handle the mmio access to these > registers in QEMU emulation rather than in guest. > > To solve this issue, this series allows to expose MSI-X table > to userspace when hardware enables the capability of interrupt > remapping which can ensure that a given PCI device can only > shoot the MSIs assigned for it. And we introduce a new bus_flags > PCI_BUS_FLAGS_MSI_REMAP to test this capability on PCI side > for different archs. > > > This is based on sha1 > 26c5cebfdb6c "Merge branch 'parisc-4.13-4' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux" > > Please comment. Thanks. > > Changelog: > > v5: > * redid the whole thing via so-called IOMMU group capabilities > > v4: > * rebased on recent upstream > * got all 6 patches from v2 (v3 was missing some) > > > > > Alexey Kardashevskiy (5): > iommu: Add capabilities to a group > iommu: Set IOMMU_GROUP_CAP_ISOLATE_MSIX if MSI controller enables IRQ > remapping > iommu/intel/amd: Set IOMMU_GROUP_CAP_ISOLATE_MSIX if IRQ remapping is > enabled > powerpc/iommu: Set IOMMU_GROUP_CAP_ISOLATE_MSIX > vfio-pci: Allow to expose MSI-X table to userspace when safe > > include/linux/iommu.h | 20 ++++++++++++++++++++ > include/linux/vfio.h | 1 + > arch/powerpc/kernel/iommu.c | 1 + > drivers/iommu/amd_iommu.c | 3 +++ > drivers/iommu/intel-iommu.c | 3 +++ > drivers/iommu/iommu.c | 35 +++++++++++++++++++++++++++++++++++ > drivers/vfio/pci/vfio_pci.c | 20 +++++++++++++++++--- > drivers/vfio/pci/vfio_pci_rdwr.c | 5 ++++- > drivers/vfio/vfio.c | 15 +++++++++++++++ > 9 files changed, 99 insertions(+), 4 deletions(-) > -- Alexey