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Fri, 27 Sep 2019 14:46:17 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 23C33C605F; Fri, 27 Sep 2019 14:46:09 +0000 (GMT) Received: from leobras.br.ibm.com (unknown [9.18.235.58]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 27 Sep 2019 14:46:09 +0000 (GMT) Message-ID: <8fe1ee1abf52719e75902dc7d5cd1e91751eaba7.camel@linux.ibm.com> Subject: Re: [PATCH v3 00/11] Introduces new count-based method for monitoring lockless pagetable walks From: Leonardo Bras To: jhubbard@nvidia.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, kvm-ppc@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org Date: Fri, 27 Sep 2019 11:46:04 -0300 Content-Type: multipart/signed; micalg="pgp-sha256"; protocol="application/pgp-signature"; boundary="=-0SqJjAld2WmMrSAcbuQn" User-Agent: Evolution 3.30.5 (3.30.5-1.fc29) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-09-27_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1909270138 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: keith.busch@intel.com, tglx@linutronix.de, arnd@arndb.de, gregkh@linuxfoundation.org, yuehaibing@huawei.com, npiggin@gmail.com, rppt@linux.ibm.com, mahesh@linux.vnet.ibm.com, jgg@ziepe.ca, paulus@samba.org, aneesh.kumar@linux.ibm.com, ganeshgr@linux.ibm.com, akpm@linux-foundation.org, ira.weiny@intel.com, dan.j.williams@intel.com, allison@lohutok.net Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" --=-0SqJjAld2WmMrSAcbuQn Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable John Hubbard writes: > Hi Leonardo, > > Thanks for adding linux-mm to CC for this next round of reviews. For the = benefit > of any new reviewers, I'd like to add that there are some issues that wer= e discovered > while reviewing the v2 patchset, that are not (yet) addressed in this v3 = series. > Since those issues are not listed in the cover letter above, I'll list th= em here Thanks for bringing that. The cover letter is a great place to put this info, I will keep that in mind for future patchsets. > > 1. The locking model requires a combination of disabling interrupts and > atomic counting and memory barriers, but > > a) some memory barriers are missing > (start/end_lockless_pgtbl_walk), and It seems that it works fine today because of the amount of intructions executed between the irq_disable / start_lockless_pgtbl_walk and where the THP collapse/split can happen. (It's very unlikely that it reorders that much). But I don't think it would be so bad to put a memory barrier after irq_disable just in case. > b) some cases (patch #8) fail to disable interrupts I have done some looking into that, and it seems that some uses of {start,end}_lockless_pgtbl_walk are unneeded, because they operate in (nested) guest pgd and I was told it's safe against THP split/collapse. In other uses, there is no interrupt disable because the function is called in real mode, with MSR_EE=3D0, and there we have instructions disabled, so there is no need to disable them again. > > ...so the synchronization appears to be inadequate. (And if it *is* adequ= ate, then > definitely we need the next item, to explain it.) > > 2. Documentation of the synchronization/locking model needs to exist, onc= e we > figure out the exact details of (1). I will add the missing doc in the code, so it may be easier to understand in the future. > > 3. Related to (1), I've asked to change things so that interrupt controls= and=20 > atomic inc/dec are in the same start/end calls--assuming, of course, that= the > caller can tolerate that.=20 I am not sure if it would be ok to use irq_{save,restore} in real mode, I will do some more reading of the docs before addressing this.=20 > > 4. Please see the v2 series for any other details I've missed. > > thanks, > --=20 > John Hubbard > NVIDIA > Thank you for helping, John! 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