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From: Kumar Gala <kumar.gala@freescale.com>
Date: Mon, 25 Apr 2005 16:39:56 -0500
To: "Stuart Yoder" <stuart.yoder@conformative.com>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: PowerPC + SMP
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On Apr 25, 2005, at 4:10 PM, Stuart Yoder wrote:

> Hi.
> =A0
> I am trying to figure out where in the PowerPC kernel the HID1=20
> register is updated to enable bits dealing with cache coherency in an=20=

> SMP system.=A0=A0 Grepping through the arch/ppc source does not reveal=20=

> much.
> =A0
> I have=A0two 7447A processors and somewhere the ABE and SYNCBE bits in=20=

> HID1=A0need to be turned on to enable cache coherency.=A0=A0 Is =
supposed to=20
> happen in the bootloader prior to the kernel running??

The expectation is that the bootloader normally handles such things.

- kumar