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Message-ID: <94202834-6151-03ad-8891-d460a60e5e15@linux.intel.com>
Date: Wed, 4 Jan 2023 18:34:19 +0530
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Subject: Re: [PATCH] PCI/AER: Rate limit the reporting of the correctable
 errors
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To: Leon Romanovsky <leon@kernel.org>
References: <20230103191418.GA1011392@bhelgaas>
 <e6e53119-a249-a03f-c9eb-3caafbe5d983@linux.intel.com>
 <Y7Ug3F6AIhaAiqCD@unreal>
From: Rajat Khandelwal <rajat.khandelwal@linux.intel.com>
In-Reply-To: <Y7Ug3F6AIhaAiqCD@unreal>
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Cc: Paul Menzel <pmenzel@molgen.mpg.de>, "Neftin, Sasha" <sasha.neftin@intel.com>, linux-pci@vger.kernel.org, Frederick Zhang <frederick888@tsundere.moe>, rajat.khandelwal@intel.com, linux-kernel@vger.kernel.org, oohall@gmail.com, bhelgaas@google.com, Bjorn Helgaas <helgaas@kernel.org>, linuxppc-dev@lists.ozlabs.org
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Hi Leon,
Thanks for the ack.

On 1/4/2023 12:16 PM, Leon Romanovsky wrote:
> On Wed, Jan 04, 2023 at 10:27:33AM +0530, Rajat Khandelwal wrote:
>> Hi Bjorn,
>>
>> Thanks for the acknowledgement.
>>
>> On 1/4/2023 12:44 AM, Bjorn Helgaas wrote:
>>> [+cc Paul, Sasha, Leon, Frederick]
>>>
>>> (Please cc folks who have commented on previous versions of your
>>> patch.)
>>>
>>> On Tue, Jan 03, 2023 at 10:25:48PM +0530, Rajat Khandelwal wrote:
>>>> There are many instances where correctable errors tend to inundate
>>>> the message buffer. We observe such instances during thunderbolt PCIe
>>>> tunneling.
> <...>
>
>>>> [54982.838808] igc 0000:2b:00.0:   device [8086:5502] error status/mask=00001000/00002000
>>>> [54982.838817] igc 0000:2b:00.0:    [12] Timeout
>>> Please remove the timestamps; they don't contribute to understanding
>>> the problem.
>> --> Sure.
> Please don't add "-->" or any marker to replies. It breaks mail color
> scheme.
>
>>>> This gets repeated continuously, thus inundating the buffer.
>>> Did you verify that we actually clear the Correctable Error Status
>>> register?
>> --> This patch targets only rate limiting the correctable errors since they are
>> non-fatal, and they kind of inundate the CPU logs, particularly during thunderbolt
>> connections. It doesn't have an impact anywhere else.
>> As per your suggestion in the igc patch, I found rate limiting as a doable option
>> currently. Have eradicated any kind of masking the bits.
> You didn't answer on the asked question. "Did you verify that we actually clear
> the Correctable Error Status register?".

Yes, I have verified. The status is cleared successfully.

>
> Thanks
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    <pre>Hi Leon,
Thanks for the ack.
</pre>
    <div class="moz-cite-prefix">On 1/4/2023 12:16 PM, Leon Romanovsky
      wrote:<br>
    </div>
    <blockquote type="cite" cite="mid:Y7Ug3F6AIhaAiqCD@unreal">
      <pre class="moz-quote-pre" wrap="">On Wed, Jan 04, 2023 at 10:27:33AM +0530, Rajat Khandelwal wrote:
</pre>
      <blockquote type="cite">
        <pre class="moz-quote-pre" wrap="">Hi Bjorn,

Thanks for the acknowledgement.

On 1/4/2023 12:44 AM, Bjorn Helgaas wrote:
</pre>
        <blockquote type="cite">
          <pre class="moz-quote-pre" wrap="">[+cc Paul, Sasha, Leon, Frederick]

(Please cc folks who have commented on previous versions of your
patch.)

On Tue, Jan 03, 2023 at 10:25:48PM +0530, Rajat Khandelwal wrote:
</pre>
          <blockquote type="cite">
            <pre class="moz-quote-pre" wrap="">There are many instances where correctable errors tend to inundate
the message buffer. We observe such instances during thunderbolt PCIe
tunneling.
</pre>
          </blockquote>
        </blockquote>
      </blockquote>
      <pre class="moz-quote-pre" wrap="">
&lt;...&gt;

</pre>
      <blockquote type="cite">
        <blockquote type="cite">
          <blockquote type="cite">
            <pre class="moz-quote-pre" wrap="">[54982.838808] igc 0000:2b:00.0:   device [8086:5502] error status/mask=00001000/00002000
[54982.838817] igc 0000:2b:00.0:    [12] Timeout
</pre>
          </blockquote>
          <pre class="moz-quote-pre" wrap="">Please remove the timestamps; they don't contribute to understanding
the problem.
</pre>
        </blockquote>
        <pre class="moz-quote-pre" wrap="">
--&gt; Sure.
</pre>
      </blockquote>
      <pre class="moz-quote-pre" wrap="">
Please don't add "--&gt;" or any marker to replies. It breaks mail color
scheme.

</pre>
      <blockquote type="cite">
        <pre class="moz-quote-pre" wrap="">
</pre>
        <blockquote type="cite">
          <pre class="moz-quote-pre" wrap="">
</pre>
          <blockquote type="cite">
            <pre class="moz-quote-pre" wrap="">This gets repeated continuously, thus inundating the buffer.
</pre>
          </blockquote>
          <pre class="moz-quote-pre" wrap="">Did you verify that we actually clear the Correctable Error Status
register?
</pre>
        </blockquote>
        <pre class="moz-quote-pre" wrap="">
--&gt; This patch targets only rate limiting the correctable errors since they are
non-fatal, and they kind of inundate the CPU logs, particularly during thunderbolt
connections. It doesn't have an impact anywhere else.
As per your suggestion in the igc patch, I found rate limiting as a doable option
currently. Have eradicated any kind of masking the bits.
</pre>
      </blockquote>
      <pre class="moz-quote-pre" wrap="">
You didn't answer on the asked question. "Did you verify that we actually clear
the Correctable Error Status register?".</pre>
    </blockquote>
    <pre>Yes, I have verified. The status is cleared successfully.
</pre>
    <blockquote type="cite" cite="mid:Y7Ug3F6AIhaAiqCD@unreal">
      <pre class="moz-quote-pre" wrap="">

Thanks
</pre>
    </blockquote>
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