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Wed, 25 Aug 2021 11:03:44 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D7857AE422; Wed, 25 Aug 2021 11:03:41 +0000 (GMT) Received: from li-c7b85bcc-2727-11b2-a85c-a9ba7f3a2193.ibm.com (unknown [9.43.52.60]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 25 Aug 2021 11:03:41 +0000 (GMT) Subject: Re: [PATCH v2 1/3] powerpc/pseries: Parse control memory access error To: Michael Ellerman , linuxppc-dev@lists.ozlabs.org References: <20210805092025.272871-1-ganeshgr@linux.ibm.com> <87eeajcpmq.fsf@mpe.ellerman.id.au> From: Ganesh Message-ID: <9734b599-eb00-a1d6-cd3c-ed6d0441f240@linux.ibm.com> Date: Wed, 25 Aug 2021 16:33:40 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <87eeajcpmq.fsf@mpe.ellerman.id.au> Content-Type: multipart/alternative; boundary="------------36E6B48FEAC961647B5A90F4" Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-GUID: ENR2cFPhssmkWK9EuxxtUNv8SLwGu2NY X-Proofpoint-ORIG-GUID: 1CZs97s0STgCQzze1Ws8735bobIlEZDb X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-25_04:2021-08-25, 2021-08-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108250066 X-Mailman-Approved-At: Wed, 25 Aug 2021 22:42:10 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, mahesh@linux.ibm.com, npiggin@gmail.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" This is a multi-part message in MIME format. --------------36E6B48FEAC961647B5A90F4 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit On 8/24/21 12:09 PM, Michael Ellerman wrote: > Hi Ganesh, > > Some comments below ... > > Ganesh Goudar writes: >> Add support to parse and log control memory access >> error for pseries. >> >> Signed-off-by: Ganesh Goudar >> --- >> v2: No changes in this patch. >> --- >> arch/powerpc/platforms/pseries/ras.c | 21 +++++++++++++++++++++ >> 1 file changed, 21 insertions(+) >> >> diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c >> index 167f2e1b8d39..608c35cad0c3 100644 >> --- a/arch/powerpc/platforms/pseries/ras.c >> +++ b/arch/powerpc/platforms/pseries/ras.c >> @@ -80,6 +80,7 @@ struct pseries_mc_errorlog { >> #define MC_ERROR_TYPE_TLB 0x04 >> #define MC_ERROR_TYPE_D_CACHE 0x05 >> #define MC_ERROR_TYPE_I_CACHE 0x07 >> +#define MC_ERROR_TYPE_CTRL_MEM_ACCESS 0x08 > ... >> >> +#define MC_ERROR_CTRL_MEM_ACCESS_PTABLE_WALK 0 >> +#define MC_ERROR_CTRL_MEM_ACCESS_OP_ACCESS 1 > > Where do the above values come from? It is from latest PAPR that added support for control memory error. >> + >> static inline u8 rtas_mc_error_sub_type(const struct pseries_mc_errorlog *mlog) >> { >> switch (mlog->error_type) { >> @@ -112,6 +116,8 @@ static inline u8 rtas_mc_error_sub_type(const struct pseries_mc_errorlog *mlog) >> case MC_ERROR_TYPE_ERAT: >> case MC_ERROR_TYPE_TLB: >> return (mlog->sub_err_type & 0x03); >> + case MC_ERROR_TYPE_CTRL_MEM_ACCESS: >> + return (mlog->sub_err_type & 0x70) >> 4; > Can you add to the comment above sub_err_type explaining what these bits are. Sure, for other errors it is explained in pseries_mc_errorlog definition, ill add it there. >> default: >> return 0; >> } >> @@ -699,6 +705,21 @@ static int mce_handle_err_virtmode(struct pt_regs *regs, >> case MC_ERROR_TYPE_I_CACHE: >> mce_err.error_type = MCE_ERROR_TYPE_ICACHE; >> break; >> + case MC_ERROR_TYPE_CTRL_MEM_ACCESS: >> + mce_err.error_type = MCE_ERROR_TYPE_RA; >> + if (mce_log->sub_err_type & 0x80) > This appears many times in the file. > > Can we add eg. MC_EFFECTIVE_ADDR_PROVIDED? ok, thanks. >> + eaddr = be64_to_cpu(mce_log->effective_address); >> + switch (err_sub_type) { >> + case MC_ERROR_CTRL_MEM_ACCESS_PTABLE_WALK: >> + mce_err.u.ra_error_type = >> + MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN; > That name is ridiculously long, but I guess that's not your fault :) > We can fix it up in a later patch. > >> + break; >> + case MC_ERROR_CTRL_MEM_ACCESS_OP_ACCESS: >> + mce_err.u.ra_error_type = >> + MCE_RA_ERROR_LOAD_STORE_FOREIGN; >> + break; >> + } >> + break; > cheers --------------36E6B48FEAC961647B5A90F4 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 7bit


On 8/24/21 12:09 PM, Michael Ellerman wrote:
Hi Ganesh,

Some comments below ...

Ganesh Goudar <ganeshgr@linux.ibm.com> writes:
Add support to parse and log control memory access
error for pseries.

Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com>
---
v2: No changes in this patch.
---
 arch/powerpc/platforms/pseries/ras.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index 167f2e1b8d39..608c35cad0c3 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -80,6 +80,7 @@ struct pseries_mc_errorlog {
 #define MC_ERROR_TYPE_TLB		0x04
 #define MC_ERROR_TYPE_D_CACHE		0x05
 #define MC_ERROR_TYPE_I_CACHE		0x07
+#define MC_ERROR_TYPE_CTRL_MEM_ACCESS	0x08
...
 
+#define MC_ERROR_CTRL_MEM_ACCESS_PTABLE_WALK	0
+#define MC_ERROR_CTRL_MEM_ACCESS_OP_ACCESS	1

Where do the above values come from?
It is from latest PAPR that added support for control memory error.
+
 static inline u8 rtas_mc_error_sub_type(const struct pseries_mc_errorlog *mlog)
 {
 	switch (mlog->error_type) {
@@ -112,6 +116,8 @@ static inline u8 rtas_mc_error_sub_type(const struct pseries_mc_errorlog *mlog)
 	case	MC_ERROR_TYPE_ERAT:
 	case	MC_ERROR_TYPE_TLB:
 		return (mlog->sub_err_type & 0x03);
+	case	MC_ERROR_TYPE_CTRL_MEM_ACCESS:
+		return (mlog->sub_err_type & 0x70) >> 4;
Can you add to the comment above sub_err_type explaining what these bits are.
Sure, for other errors it is explained in pseries_mc_errorlog definition, ill add it there. 
 	default:
 		return 0;
 	}
@@ -699,6 +705,21 @@ static int mce_handle_err_virtmode(struct pt_regs *regs,
 	case MC_ERROR_TYPE_I_CACHE:
 		mce_err.error_type = MCE_ERROR_TYPE_ICACHE;
 		break;
+	case MC_ERROR_TYPE_CTRL_MEM_ACCESS:
+		mce_err.error_type = MCE_ERROR_TYPE_RA;
+		if (mce_log->sub_err_type & 0x80)
This appears many times in the file.

Can we add eg. MC_EFFECTIVE_ADDR_PROVIDED?
ok, thanks.
+			eaddr = be64_to_cpu(mce_log->effective_address);
+		switch (err_sub_type) {
+		case MC_ERROR_CTRL_MEM_ACCESS_PTABLE_WALK:
+			mce_err.u.ra_error_type =
+				MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN;
That name is ridiculously long, but I guess that's not your fault :)
We can fix it up in a later patch.

+			break;
+		case MC_ERROR_CTRL_MEM_ACCESS_OP_ACCESS:
+			mce_err.u.ra_error_type =
+				MCE_RA_ERROR_LOAD_STORE_FOREIGN;
+			break;
+		}
+		break;
cheers
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