Re: Trouble "Transferring control to Linux (at address 00000000)"

[Mikhail Zaturenskiy <mzaturenskiy.st@gmail.com>]

[-- Attachment #1: Type: text/plain, Size: 8010 bytes --]

Hi guys, I've been working off your suggestions and here's my update
on where I'm at now.

For reference, attached are my current
"linux-2.6-denx/arch/powerpc/boot/dts/ep88xc.dts" and
"u-boot-2009.03/include/configs/EP88x.h".

> I might be able to help out. Scott's right. According to U-Boots
> include/configs/EP88x.h,
> CONFIG_SYS_IMMR is 0xf0000000, but the Linux the ep88xc.dts is
> referring to an IMMR set
> to 0xfa200000. Replace every instance of 0xfa20 with 0xf000, and it may work.
I did notice the IMMR discrepancy and as Frank suggested adjusted the
0xfa20xxxx values to 0xf000xxxx in my DTS, though I'm wondering if it
would be better to have just set my CONFIG_SYS_IMMR to 0xfa200000? Not
sure if that would break more than it would fix. Anyways, I have not
noticed any difference in output after changing this in the DTS, but
I'll leave it this way as it seems more correct.

>>> Also, make sure u-boot is properly updating the memory size in the device
>>> tree.  Can you dump the post-fixup device tree in u-boot?
>> Not sure, but I'll try to find out if that's possible. It'd certainly
>> answer a lot of questions...
While I have not yet figured out how to dump the post-fixup tree... I
can see that U-Boot doesn't seem to be doing proper fixup because
after manually setting all the DTS fields that U-Boot was supposed to
fill in (clock frequency, RAM start/end, etc.), the kernel seems to be
going through a fairly normal boot sequence. Without me manually
setting those fields, they remain initialized to 0. The only issue is
that no output goes to the console.

Here is my current output.
>From U-Boot:

U-Boot 2009.03-svn8591 (Jun 29 2009 - 11:25:23)

CPU:   MPC885ZPnn at 100 MHz [40.0...133.0 MHz]
       8 kB I-Cache 8 kB D-Cache FEC present
Board: EP88xC 1.1  CPLD revision 2
DRAM:  64 MB
FLASH: 32 MB
In:    serial
Out:   serial
Err:   serial
Net:   FEC ETHERNET, FEC2 ETHERNET
Hit any key to stop autoboot:  0
=> tftp ep88x_uimage2
Using FEC ETHERNET device
TFTP from server 10.0.54.129; our IP address is 10.0.54.150
Filename 'ep88x_uimage2'.
Load address: 0x400000
Loading: #################################################################
         ########
done
Bytes transferred = 1057419 (10228b hex)
=> tftp 750000 ep88x_dtb2
Using FEC ETHERNET device
TFTP from server 10.0.54.129; our IP address is 10.0.54.150
Filename 'ep88x_dtb2'.
Load address: 0x750000
Loading: #
done
Bytes transferred = 7725 (1e2d hex)
=> bootm 400000 - 750000
## Booting kernel from Legacy Image at 00400000 ...
   Image Name:   Linux-2.6.30-rc2-01402-gd4e2f68-
   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
   Data Size:    1057355 Bytes =  1 MB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 00750000
   Booting using the fdt blob at 0x750000
   Uncompressing Kernel Image ... OK


>From Kernel via postmortem analysis - sorry it's a little messy, my
debugger ICDPPCZ is not that great at producing memory dumps so I had
to do some cleanup/conversion to make the results at least somewhat
legible:

<6>Using Embedded Planet EP88xC machine description?
<5>Linux version 2.6.30-rc2-??1402-gd4e2f68-dirty
(devone@localhost.localdomain) (gcc version 4.2.2) #1 Mon J??n 29
11:35:28 CDT 2009?
<7>Top of RAM: 0x4000000' Total RAM: 0x4000000?
<7>Memory??hole size: 0MB?
<4>Zone PFN ranges:?
<4>  DMA      0x00000000 -> 0x00004000?
<4>  ??ormal   0x00004000 -> 0x00004000?
<4>Movable zone start PFN for each node?
<4>ear??y_node_map[1] active PFN ranges?
<4>    0: 0x00000000 -> 0x00004000?
<7>On node 0??totalpages: 16384?
<7>free_area_init_node: node 0' pgdat c021bf7c' node_mem_map ??023f000?
<7>  DMA zone: 128 pages used for memmap?
<7>  DMA zone: 0 pages reserve???
<7>  DMA zone: 16256 pages' LIFO batch:3?
<6>MMU: Allocated 72 bytes of context??maps for 16 contexts?
<4>Built 1 zonelists in Zone order' mobility grouping on. ??Total pages: 16256?
<5>Kernel command line: console=ttyS0'9600n8 loglevel=7?
<6>N??_IRQS:512?
<7>irq: irq 5 on host /soc@f0000000/interrupt-controller@0 mapped to
??irtual irq 16?
<7>irq: irq 0 on host /soc@f0000000/cpm@9c0/interrupt-controller@??30
mapped to virtual irq 17?
<4>PID hash table entries: 256 (order: 8' 1024 byte??)?
<4>Decrementer Frequency = 0x7bfa48?
<7>irq: irq 15 on host /soc@f0000000/inte??rupt-controller@0 mapped to
virtual irq 18?
<7>time_init: decrementer frequency ?? 8.125000 MHz?
<7>time_init: processor frequency   = 130.000000 MHz?
<6>clocksour??e: timebase mult[1ec4ec4f] shift[22] registered?
<7>clockevent: decrementer mult??214] shift[16] cpu[0]?
<6>Dentry cache hash table entries: 8192 (order: 3' 32768??bytes)?
<6>Inode-cache hash table entries: 4096 (order: 2' 16384 bytes)?
<6>Memor??: 62532k/65536k available (2064k kernel code' 2940k
reserved' 100k data' 99k bs??' 96k init)?
<6>SLUB: Genslabs=12' HWalign=16' Order=0-3' MinObjects=0' CPUs=1' ??odes=1?
<6>Calibrating delay loop... 16.12 BogoMIPS (lpj=80640)?
<4>Mount-cache h??sh table entries: 512?
<6>net_namespace: 296 bytes?
<6>NET: Registered protocol f??mily 16?
<4>bio: create slab <bio-0> at 0?
<7>Switched to high resolution mode on??CPU 0?
<6>NET: Registered protocol family 2?
<6>IP route cache hash table entries?? 1024 (order: 0' 4096 bytes)?
<6>TCP established hash table entries: 2048 (order?? 2' 16384 bytes)?
<6>TCP bind hash table entries: 2048 (order: 1' 8192 bytes)?
<6??TCP: Hash tables configured (established 2048 bind 2048)?
<6>TCP reno registered??
<6>NET: Registered protocol family 1?
<6>msgmni has been set to 122?
<6>io schedu??er noop registered?
<6>io scheduler deadline registered (default)?
<6>Generic RTC??Driver v1.07?
<7>irq: irq 4 on host /soc@f0000000/cpm@9c0/interrupt-controller@9??0
mapped to virtual irq 19?
<6>f0000a80.serial: ttyCPM0 at MMIO 0xc500ea80 (irq ?? 19) is a CPM UART?
<7>irq: irq 29 on host /soc@f0000000/cpm@9c0/interrupt-contr??ller@930
mapped to virtual irq 29?
<6>f0000a20.serial: ttyCPM1 at MMIO 0xc501aa2?? (irq = 29) is a CPM UART?
<7>irq: irq 3 on host /soc@f0000000/interrupt-control??er@0 mapped to
virtual irq 20?
<6>eth0: fs_enet: 00:00:00:00:00:00?
<7>irq: irq 7??on host /soc@f0000000/interrupt-controller@0 mapped to
virtual irq 21?
<6>eth1: ??s_enet: 00:00:00:00:00:00?
<6>FEC MII Bus: probed?
<6>fe000000.flash: Found 2 x16??devices at 0x0 in 32-bit bank?
<4> Amd/Fujitsu Extended Query Table at 0x0040?
<4??fe000000.flash: CFI does not contain boot bank location. Assuming top.?
<5>numbe?? of CFI chips: 1?
<5>cfi_cmdset_0002: Disabling erase-suspend-program due to cod?? brokenness.?
<6>TCP cubic registered?
<6>NET: Registered protocol family 17?
<6>R??C: Registered udp transport module.?
<6>RPC: Registered tcp transport module.?
<3??Root-NFS: No NFS server available' giving up.?
<3>VFS: Unable to mount root fs v??a NFS' trying floppy.?
<4>VFS: Cannot open root device "<NULL>" or unknown-block??2'0)?
<4>Please append a correct "root=" boot option; here are the available
par??itions:?
<4>1f00           32768 mtdblock0 driver: of-flash?
<0>Kernel panic - no?? syncing: VFS: Unable to mount root fs on
unknown-block(2'0)?
<4>Call Trace:?
<4>??c381fed0] [c00069e0] show_stack+0x44/0x16c (unreliable)?
<4>[c381ff10] [c001bc6c?? panic+0x8c/0x168?
<4>[c381ff60] [c01ecb80] mount_block_root+0x12c/0x244?
<4>[c38??ffb0] [c01ecdf4] prepare_namespace+0x4c/0x1c4?
<4>[c381ffd0] [c01ec1b0] kernel_i??it+0xd0/0xfc?
<4>[c381fff0] [c000da60] kernel_thread+0x4c/0x68?
<0>Rebooting in 1??0 seconds..?????????????????????????????????

At this point, my primary goal is to get console output working before
I do anything else. I've tried different "console=x" boot arguments
and I've added the "chosen" section to my DTS, but still no output.
Anyone have suggestions about this? Is something else messed up in my
DTS?

Thanks,
Mikhail Zaturenskiy

[-- Attachment #2: ep88xc.dts --]
[-- Type: application/octet-stream, Size: 5101 bytes --]

/*
 * EP88xC Device Tree Source
 *
 * Copyright 2006 MontaVista Software, Inc.
 * Copyright 2007,2008 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "EP88xC";
	compatible = "fsl,ep88xc";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,885@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <16>;
			i-cache-line-size = <16>;
			d-cache-size = <8192>;
			i-cache-size = <8192>;
			timebase-frequency = <8000000>; // MZ - was 0
			bus-frequency = <50000000>; // MZ - was 0
			clock-frequency = <130000000>; // MZ - was 0,
			interrupts = <15 2>;	// decrementer interrupt
			interrupt-parent = <&PIC>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x04000000>; // MZ - was <0x0 0x0>
	};

	localbus@f0000100 { // MZ - was fa20xxxx
		compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
		#address-cells = <2>;
		#size-cells = <1>;
		reg = <0xf0000100 0x40>; // MZ - was fa20xxxx

		ranges = <
			0x0 0x0 0xfc000000 0x4000000
			0x3 0x0 0xfa000000 0x1000000
		>;

		flash@0,2000000 {
			compatible = "cfi-flash";
			reg = <0x0 0x2000000 0x2000000>;
			bank-width = <4>;
			device-width = <2>;
		};

		board-control@3,400000 {
			reg = <0x3 0x400000 0x10>;
			compatible = "fsl,ep88xc-bcsr";
		};
	};

	soc@f0000000 { // MZ - was fa20xxxx
		compatible = "fsl,mpc885", "fsl,pq1-soc";
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xf0000000 0x4000>; // MZ - was fa20xxxx
		bus-frequency = <0>;

		// Temporary -- will go away once kernel uses ranges for get_immrbase().
		reg = <0xf0000000 0x4000>; // MZ - was fa20xxxx

		mdio@e00 {
			compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
			reg = <0xe00 0x188>;
			#address-cells = <1>;
			#size-cells = <0>;

			PHY0: ethernet-phy@0 {
				reg = <0x0>;
				device_type = "ethernet-phy";
			};

			PHY1: ethernet-phy@1 {
				reg = <0x1>;
				device_type = "ethernet-phy";
			};
		};

		ethernet@e00 {
			device_type = "network";
			compatible = "fsl,mpc885-fec-enet",
			             "fsl,pq1-fec-enet";
			reg = <0xe00 0x188>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <3 1>;
			interrupt-parent = <&PIC>;
			phy-handle = <&PHY0>;
			linux,network-index = <0>;
		};

		ethernet@1e00 {
			device_type = "network";
			compatible = "fsl,mpc885-fec-enet",
			             "fsl,pq1-fec-enet";
			reg = <0x1e00 0x188>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <7 1>;
			interrupt-parent = <&PIC>;
			phy-handle = <&PHY1>;
			linux,network-index = <1>;
		};

		PIC: interrupt-controller@0 {
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x0 0x24>;
			compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
		};

		pcmcia@80 {
			#address-cells = <3>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			compatible = "fsl,pq-pcmcia";
			device_type = "pcmcia";
			reg = <0x80 0x80>;
			interrupt-parent = <&PIC>;
			interrupts = <13 1>;
		};

		cpm@9c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc885-cpm", "fsl,cpm1";
			command-proc = <0x9c0>;
			interrupts = <0>;	// cpm error interrupt
			interrupt-parent = <&CPM_PIC>;
			reg = <0x9c0 0x40>;
			ranges;

			muram@2000 {
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x2000 0x2000>;

				data@0 {
					compatible = "fsl,cpm-muram-data";
					reg = <0x0 0x1c00>;
				};
			};

			brg@9f0 {
				compatible = "fsl,mpc885-brg",
				             "fsl,cpm1-brg",
				             "fsl,cpm-brg";
				reg = <0x9f0 0x10>;
			};

			CPM_PIC: interrupt-controller@930 {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts = <5 2 0 2>;
				interrupt-parent = <&PIC>;
				reg = <0x930 0x20>;
				compatible = "fsl,mpc885-cpm-pic",
				             "fsl,cpm1-pic";
			};

			// MON-1
			serial@a80 {
				device_type = "serial";
				compatible = "fsl,mpc885-smc-uart",
				             "fsl,cpm1-smc-uart";
				reg = <0xa80 0x10 0x3e80 0x40>;
				interrupts = <4>;
				interrupt-parent = <&CPM_PIC>;
				fsl,cpm-brg = <1>;
				fsl,cpm-command = <0x90>;
				linux,planetcore-label = "SMC1";
			};

			// SER-1
			serial@a20 {
				device_type = "serial";
				compatible = "fsl,mpc885-scc-uart",
				             "fsl,cpm1-scc-uart";
				reg = <0xa20 0x20 0x3d00 0x80>;
				interrupts = <29>;
				interrupt-parent = <&CPM_PIC>;
				fsl,cpm-brg = <2>;
				fsl,cpm-command = <0x40>;
				linux,planetcore-label = "SCC2";
			};

			usb@a00 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,mpc885-usb",
				             "fsl,cpm1-usb";
				reg = <0xa00 0x18 0x1c00 0x80>;
				interrupt-parent = <&CPM_PIC>;
				interrupts = <30>;
				fsl,cpm-command = <0000>;
			};
		};
	};

	chosen {
		linux,stdout-path = "/soc@f0000000/cpm@9c0/serial@a80"; // MZ - added this 'chosen' section
	};

};

[-- Attachment #3: EP88x.h --]
[-- Type: application/octet-stream, Size: 8237 bytes --]

/*
 * Copyright (C) 2005 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * Support for Embedded Planet EP88x boards.
 * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __CONFIG_H
#define __CONFIG_H

//#define DEBUG // MZ

#define CONFIG_OF_LIBFDT 	// MZ - added to support FDT, suggested by Detlev

#define CONFIG_MPC885

#define CONFIG_EP88X				/* Embedded Planet EP88x board	*/

#define CONFIG_BOARD_EARLY_INIT_F		/* Call board_early_init_f	*/

/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

#define	CONFIG_8xx_CONS_SMC1	1		/* Console is on SMC1		*/
#define CONFIG_BAUDRATE		9600

#define	CONFIG_ETHER_ON_FEC1			/* Enable Ethernet on FEC1	*/
#define	CONFIG_ETHER_ON_FEC2			/* Enable Ethernet on FEC2	*/
#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_MII_INIT		1
#define FEC_ENET
#endif /* CONFIG_FEC_ENET */

#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT	100000000
#define CONFIG_SYS_8xx_CPUCLK_MIN	40000000
#define CONFIG_SYS_8xx_CPUCLK_MAX	133000000

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING


//#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds	*/
#define CONFIG_BOOTDELAY	15		/* MZ - Autoboot after 15 seconds	*/
//#define CONFIG_BOOTCOMMAND	"bootm fe060000"	/* Autoboot command	*/
#define CONFIG_BOOTCOMMAND	"bootm fc080000"	/* MZ - Autoboot command	*/
//#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
#define CONFIG_BOOTARGS		"console=ttyS0,9600n8 loglevel=7"	// MZ

#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_LOAD_ADDR		0x400000	/* Default load address		*/

#define CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
//#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* Up to 128 Mbyte		*/
#define CONFIG_SYS_SDRAM_MAX_SIZE	0x04000000	/* MZ - Up to 64 Mbyte		*/

#define CONFIG_SYS_MAMR		0x00805000

/*
 * 4096	Up to 4096 SDRAM rows
 * 1000	factor s -> ms
 * 32	PTP (pre-divider from MPTPR)
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CONFIG_SYS_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/

#define CONFIG_SYS_RESET_ADDRESS	0x09900000

/*-----------------------------------------------------------------------
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
#undef CONFIG_BZIP2	// MZ
#ifdef CONFIG_BZIP2
#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve ~4 MB for malloc()   */
#else
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
#endif /* CONFIG_BZIP2 */

/*-----------------------------------------------------------------------
 * Flash organisation
 */
#define CONFIG_SYS_FLASH_BASE		0xFC000000
#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
//#define CONFIG_SYS_MAX_FLASH_SECT	512		/* Max num of sects on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* MZ - Max num of sects on one chip */

/* Environment is in flash */
#define CONFIG_ENV_IS_IN_FLASH
//#define CONFIG_ENV_SECT_SIZE	0x20000		/* We use one complete sector	*/
#define CONFIG_ENV_SECT_SIZE	0x40000		/* MZ - We use one complete sector	*/ 
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)

#define CONFIG_SYS_OR0_PRELIM		0xFC000160
#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)

#define	CONFIG_SYS_DIRECT_FLASH_TFTP

/*-----------------------------------------------------------------------
 * BCSR
 */
#define CONFIG_SYS_OR3_PRELIM		0xFF0005B0
#define CONFIG_SYS_BR3_PRELIM		(0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)

#define CONFIG_SYS_BCSR		0xFA400000

/*-----------------------------------------------------------------------
 * Internal Memory Map Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Configuration registers
 */
#ifdef CONFIG_WATCHDOG
#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
				 SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
				 SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
				 SYPCR_SWF  | SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

#define CONFIG_SYS_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)

/* TBSCR - Time Base Status and Control Register */
#define CONFIG_SYS_TBSCR		(TBSCR_TBF | TBSCR_TBE)

/* PISCR - Periodic Interrupt Status and Control */
#define CONFIG_SYS_PISCR		PISCR_PS

/* SCCR - System Clock and reset Control Register */
#define SCCR_MASK		SCCR_EBDF11
#define CONFIG_SYS_SCCR		SCCR_RTSEL

#define CONFIG_SYS_DER			0

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/

/*-----------------------------------------------------------------------
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from flash	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#endif /* __CONFIG_H */