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Wed, 21 Jul 2021 15:04:35 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EB2B64C05E; Wed, 21 Jul 2021 15:04:34 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 637144C040; Wed, 21 Jul 2021 15:04:34 +0000 (GMT) Received: from localhost.localdomain (unknown [9.171.74.114]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 21 Jul 2021 15:04:34 +0000 (GMT) Subject: Re: [PATCH v5 10/11] powerpc/pseries/iommu: Make use of DDW for indirect mapping To: Alexey Kardashevskiy , Leonardo Bras , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , David Gibson , kernel test robot , Nicolin Chen References: <20210716082755.428187-1-leobras.c@gmail.com> <20210716082755.428187-11-leobras.c@gmail.com> <8dfb28d5-b654-746c-03d8-aeee3d438240@ozlabs.ru> From: Frederic Barrat Message-ID: <994051df-73b3-4dad-76aa-1a03d9afaf6d@linux.ibm.com> Date: Wed, 21 Jul 2021 17:04:34 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <8dfb28d5-b654-746c-03d8-aeee3d438240@ozlabs.ru> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 64t-t_OYI5dWibQk5RuFJ-01YuYFt3K_ X-Proofpoint-ORIG-GUID: w9ni4Lr0nTcXsDyW-V2JMK6vrmnEZ72J X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-21_09:2021-07-21, 2021-07-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 mlxscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107210088 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 21/07/2021 05:32, Alexey Kardashevskiy wrote: >>> +        struct iommu_table *newtbl; >>> +        int i; >>> + >>> +        for (i = 0; i < ARRAY_SIZE(pci->phb->mem_resources); i++) { >>> +            const unsigned long mask = IORESOURCE_MEM_64 | >>> IORESOURCE_MEM; >>> + >>> +            /* Look for MMIO32 */ >>> +            if ((pci->phb->mem_resources[i].flags & mask) == >>> IORESOURCE_MEM) >>> +                break; >>> +        } >>> + >>> +        if (i == ARRAY_SIZE(pci->phb->mem_resources)) >>> +            goto out_del_list; >> >> >> So we exit and do nothing if there's no MMIO32 bar? >> Isn't the intent just to figure out the MMIO32 area to reserve it when >> init'ing the table? In which case we could default to 0,0 >> >> I'm actually not clear why we are reserving this area on pseries. > > > > If we do not reserve it, then the iommu code will allocate DMA pages > from there and these addresses are MMIO32 from the kernel pov at least. > I saw crashes when (I think) a device tried DMAing to the top 2GB of the > bus space which happened to be a some other device's BAR. hmmm... then figuring out the correct range needs more work. We could have more than one MMIO32 bar. And they don't have to be adjacent. I don't see that we are reserving any range on the initial table though (on pseries). Fred