From: Dave Hansen <dave.hansen@intel.com>
To: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>,
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>,
Srikar Dronamraju <srikar@linux.vnet.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Michael Neuling <mikey@neuling.org>,
Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>,
Akshay Adiga <akshay.adiga@linux.vnet.ibm.com>,
Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>,
Oliver O'Halloran <oohall@gmail.com>,
Nicholas Piggin <npiggin@gmail.com>,
Murilo Opsfelder Araujo <muriloo@linux.ibm.com>,
Anton Blanchard <anton@samba.org>
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 0/3] powerpc: Detection and scheduler optimization for POWER9 bigcore
Date: Mon, 1 Oct 2018 07:05:11 -0700 [thread overview]
Message-ID: <994106db-7f79-7d22-0d4e-f458bd85bb64@intel.com> (raw)
In-Reply-To: <1538399802-23582-1-git-send-email-ego@linux.vnet.ibm.com>
On 10/01/2018 06:16 AM, Gautham R. Shenoy wrote:
>
> Patch 3: Creates a pair of sysfs attributes named
> /sys/devices/system/cpu/cpuN/topology/smallcore_thread_siblings
> and
> /sys/devices/system/cpu/cpuN/topology/smallcore_thread_siblings_list
> exposing the small-core siblings that share the L1 cache
> to the userspace.
I really don't think you've justified the existence of a new user/kernel
interface here. We already have information about threads share L1
caches in here:
/sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_list
The only question would be if anything would break because it assumes
that all SMT siblings share all caches. But, it breaks if your new
interface is there or not; it's old software that we care about.
next prev parent reply other threads:[~2018-10-01 14:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-01 13:16 [PATCH v9 0/3] powerpc: Detection and scheduler optimization for POWER9 bigcore Gautham R. Shenoy
2018-10-01 13:16 ` [PATCH v9 1/3] powerpc: Detect the presence of big-cores via "ibm, thread-groups" Gautham R. Shenoy
2018-10-01 13:16 ` [PATCH v9 2/3] powerpc: Use cpu_smallcore_sibling_mask at SMT level on bigcores Gautham R. Shenoy
2018-10-01 13:16 ` [PATCH v9 3/3] powerpc/sysfs: Add topology/smallcore_thread_siblings[_list] Gautham R. Shenoy
2018-10-01 14:05 ` Dave Hansen [this message]
2018-10-03 11:19 ` [PATCH v9 0/3] powerpc: Detection and scheduler optimization for POWER9 bigcore Gautham R Shenoy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=994106db-7f79-7d22-0d4e-f458bd85bb64@intel.com \
--to=dave.hansen@intel.com \
--cc=akshay.adiga@linux.vnet.ibm.com \
--cc=aneesh.kumar@linux.ibm.com \
--cc=anton@samba.org \
--cc=benh@kernel.crashing.org \
--cc=ego@linux.vnet.ibm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mikey@neuling.org \
--cc=mpe@ellerman.id.au \
--cc=muriloo@linux.ibm.com \
--cc=npiggin@gmail.com \
--cc=oohall@gmail.com \
--cc=shilpa.bhat@linux.vnet.ibm.com \
--cc=srikar@linux.vnet.ibm.com \
--cc=svaidy@linux.vnet.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).