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From: Kumar Gala <galak@kernel.crashing.org>
Subject: Re: [PATCH] Remove CPU_FTR_NEED_COHERENT for 7448.
Date: Fri, 4 May 2007 15:19:22 -0500
To: Adrian Cox <adrian@humboldt.co.uk>
Cc: "linuxppc-dev@ozlabs.org" <linuxppc-dev@ozlabs.org>
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On May 3, 2007, at 5:17 AM, Adrian Cox wrote:

> On Wed, 2007-05-02 at 16:34 -0500, Jon Loeliger wrote:
>> From: James.Yang <James.Yang@freescale.com>
>>
>> Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx).
>> This prevents needlessly setting M=1 when not SMP.
>
> There may be side effects to removing this. Most of the 74xx  
> processors
> had this flag added because of the L2 prefetch bug (erratum #16 on the
> 7447A). I see that bug is missing from the 7448 errata.
>
> The problem is that many 32-bit PowerPC machines needed
> CPU_FTR_NEED_COHERENT set for a second reason: compatibility with the
> cache in the MPC107. This was handled by CPU_FTR_COMMON in cputable.h
> before the L2 prefetch bug was known.  There may be other host bridges
> that cache, but nobody will have noticed because all the CPUs had
> CPU_FTR_NEED_COHERENT set already.

While this may be the case for non-10X bridges I don't think we  
should impose the restriction if we don't know its actually needed.

- k