* interrupt latency spi
@ 2008-04-03 14:04 mejjad lahcen
0 siblings, 0 replies; 3+ messages in thread
From: mejjad lahcen @ 2008-04-03 14:04 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 411 bytes --]
hi all of you , I am wndering if someone has already done test for interrupt
latency on linx 2.6.23 mpc5200b.
I am working on writing a driver which is get SPi involved on design, and I
know that the spi interrupt will occurs at every 2 us ( speed 4 MHz
interupt occurs when It recieves on bytes) so I am worring about interrupt
latency.
I dont know if someone has any suggestions or a litle advice.
cheers
[-- Attachment #2: Type: text/html, Size: 482 bytes --]
^ permalink raw reply [flat|nested] 3+ messages in thread
* interrupt latency spi
@ 2008-04-03 13:09 mejjad lahcen
2008-04-03 17:41 ` Gabriel Paubert
0 siblings, 1 reply; 3+ messages in thread
From: mejjad lahcen @ 2008-04-03 13:09 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 411 bytes --]
hi all of you ,
I am wndering if someone has already done test for interrupt latency on
linx 2.6.23 mpc5200b.
I am working on writing a driver which is get SPi involved on design, and I
know that the spi interrupt will occurs at every 2 us ( speed 4 MHz
interupt occurs when It recieves on bytes) so I am worring about interrupt
latency.
I dont know if someone has any suggestions or a litle advice.
cheers
[-- Attachment #2: Type: text/html, Size: 534 bytes --]
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: interrupt latency spi
2008-04-03 13:09 mejjad lahcen
@ 2008-04-03 17:41 ` Gabriel Paubert
0 siblings, 0 replies; 3+ messages in thread
From: Gabriel Paubert @ 2008-04-03 17:41 UTC (permalink / raw)
To: mejjad lahcen; +Cc: linuxppc-dev
On Thu, Apr 03, 2008 at 09:09:04AM -0400, mejjad lahcen wrote:
> hi all of you ,
> I am wndering if someone has already done test for interrupt latency on
> linx 2.6.23 mpc5200b.
> I am working on writing a driver which is get SPi involved on design, and I
> know that the spi interrupt will occurs at every 2 us ( speed 4 MHz
> interupt occurs when It recieves on bytes) so I am worring about interrupt
> latency.
Expecting to be able to handle an interrupt every 2 microseconds is
simply crazy. Your hardware should at least have some FIFO to buffer
the data, hey, that's what UART started doing even at much lower bit
rates...
Gabriel
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2008-04-03 17:41 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-04-03 14:04 interrupt latency spi mejjad lahcen
-- strict thread matches above, loose matches on Subject: below --
2008-04-03 13:09 mejjad lahcen
2008-04-03 17:41 ` Gabriel Paubert
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).