From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from qw-out-2122.google.com (qw-out-2122.google.com [74.125.92.27]) by ozlabs.org (Postfix) with ESMTP id B8984DDF70 for ; Fri, 26 Sep 2008 04:02:10 +1000 (EST) Received: by qw-out-2122.google.com with SMTP id 9so81053qwb.15 for ; Thu, 25 Sep 2008 11:02:09 -0700 (PDT) Message-ID: <9e4733910809251102i9c87fcfrfc5ae45e90dd07f@mail.gmail.com> Date: Thu, 25 Sep 2008 14:02:08 -0400 From: "Jon Smirl" To: "Grant Likely" Subject: Re: MPC5200 PCI interrupt routing In-Reply-To: <20080925165755.GB16018@secretlab.ca> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_1888_13909867.1222365729065" References: <200809221556.34353.jbe@pengutronix.de> <20080924181542.GA9690@secretlab.ca> <1222291345.8277.92.camel@pasglop> <200809250951.15941.jbe@pengutronix.de> <20080925165755.GB16018@secretlab.ca> Cc: linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ------=_Part_1888_13909867.1222365729065 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline On Thu, Sep 25, 2008 at 12:57 PM, Grant Likely wrote: > On Thu, Sep 25, 2008 at 09:51:14AM +0200, Juergen Beisert wrote: >> Benjamin, >> >> On Mittwoch, 24. September 2008, Benjamin Herrenschmidt wrote: >> > On Wed, 2008-09-24 at 12:15 -0600, Grant Likely wrote: >> > > On Wed, Sep 24, 2008 at 05:16:34PM +0200, Juergen Beisert wrote: >> > > > On Dienstag, 23. September 2008, Juergen Beisert wrote: >> > > > > What Kernel do you run on your target? On my hardware a 2.6.23 still >> > > > > work as expected, but a 2.6.26 fails all the time. >> > > > >> > > > One should enable the internal USB clock. If done, it works... In >> > > > 2.6.23 is was done in mpc52xx_common.c. It was removed in 2.6.24. >> > > >> > > It was removed because some 5200 platform do not use USB and should not >> > > enable the internal clock. In general, it is not the kernel's job to >> > > configure clocking and pin usage on the chip. Instead, it should be set >> > > correctly at power up by U-Boot. I got the attached diagram from Freescale on how to program the divider. It's not in the user manual. Freescale is recommending a 33.333Mhz crystal for the mpc5200 now. If you use 33.3333Mhz you won't be able to set a 48Mhz internal clock. Closest you can get is 48.4848Mhz. Sticking with a 33Mhz crystal allow an accurate 48Mhz clock. Clocking USB at the wrong clock rate will make some devices not function or get errors. The new mpc5200 datasheet has removed the option of using a 16x multiplier on a 33Mhz crystal and running the core at 528Mhz. The new datasheet only allows up to 400Mhz for the core. Anyone know what is going on? -- Jon Smirl jonsmirl@gmail.com ------=_Part_1888_13909867.1222365729065 Content-Type: application/pdf; name=fractinal_div.pdf Content-Transfer-Encoding: base64 X-Attachment-Id: f_fljmwzip0 Content-Disposition: attachment; filename=fractinal_div.pdf JVBERi0xLjIKJeLjz9MNCjEwIDAgb2JqCjw8IAovTGluZWFyaXplZCAxIAovTyAxMyAKL0ggWyA3 MzMgMTczIF0gCi9MIDgzODMgCi9FIDc0NDkgCi9OIDEgCi9UIDgwNjUgCj4+IAplbmRvYmoKICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICB4cmVmCjEwIDE0IAowMDAwMDAwMDE2IDAwMDAwIG4gCjAwMDAwMDA2MjYgMDAwMDAgbiAKMDAw MDAwMDY5NSAwMDAwMCBuIAowMDAwMDAwOTA2IDAwMDAwIG4gCjAwMDAwMDEwNTkgMDAwMDAgbiAK MDAwMDAwMTE2MiAwMDAwMCBuIAowMDAwMDA0MTE2IDAwMDAwIG4gCjAwMDAwMDQzNTAgMDAwMDAg biAKMDAwMDAwNDczMyAwMDAwMCBuIAowMDAwMDA1MDY0IDAwMDAwIG4gCjAwMDAwMDU1ODEgMDAw MDAgbiAKMDAwMDAwNzMxMCAwMDAwMCBuIAowMDAwMDAwNzMzIDAwMDAwIG4gCjAwMDAwMDA4ODYg MDAwMDAgbiAKdHJhaWxlcgo8PAovU2l6ZSAyNAovSW5mbyA4IDAgUiAKL1Jvb3QgMTEgMCBSIAov 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