* [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge
@ 2012-03-06 9:06 Zhao Chenhui
2012-03-06 9:06 ` [PATCH 3/9] l2sram: Add compatible entry for mpc8548 Zhao Chenhui
` (7 more replies)
0 siblings, 8 replies; 20+ messages in thread
From: Zhao Chenhui @ 2012-03-06 9:06 UTC (permalink / raw)
To: linuxppc-dev
From: chenhui zhao <chenhui.zhao@freescale.com>
There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
southbridge chip.
The bootloader sets the PCI bridge to open a window from 0x0000
to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
resource. In the routine pci_read_bridge_io(), if the base which
is read from PCI_IO_BASE is equal to zero, the routine don't set
the I/O resource of the child bus.
To allow the legacy I/O space on the VIA southbridge to be accessed,
use the fixup to fix the PCI I/O space of the PCI bridge.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 29 +++++++++++++++++++++++++++--
1 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 40f03da..c009c5b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -3,7 +3,7 @@
*
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
*
- * Copyright 2005 Freescale Semiconductor Inc.
+ * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -158,6 +158,31 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
+/*
+ * Fix Tsi310 PCI-X bridge resource.
+ * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
+ * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
+ */
+void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
+{
+ struct pci_dev *dev = bus->self;
+ struct resource *res = bus->resource[0];
+
+ if (dev != NULL &&
+ dev->vendor == PCI_VENDOR_ID_IBM &&
+ dev->device == PCI_DEVICE_ID_IBM_PCIX_BRIDGE) {
+ if (res) {
+ res->start = 0;
+ res->end = 0x1fff;
+ res->flags = IORESOURCE_IO;
+ pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
+ pr_info("mpc85xx_cds: %pR\n", res);
+ }
+ }
+
+ fsl_pcibios_fixup_bus(bus);
+}
+
#ifdef CONFIG_PPC_I8259
static void mpc85xx_8259_cascade_handler(unsigned int irq,
struct irq_desc *desc)
@@ -323,7 +348,7 @@ define_machine(mpc85xx_cds) {
.get_irq = mpic_get_irq,
#ifdef CONFIG_PCI
.restart = mpc85xx_cds_restart,
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
#else
.restart = fsl_rstcr_restart,
#endif
--
1.6.4.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/9] l2sram: Add compatible entry for mpc8548
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
@ 2012-03-06 9:06 ` Zhao Chenhui
2012-03-06 9:06 ` [PATCH 4/9] powerpc/mpc8548cds: Add NOR flash node to dts Zhao Chenhui
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Zhao Chenhui @ 2012-03-06 9:06 UTC (permalink / raw)
To: linuxppc-dev
From: chenhui zhao <chenhui.zhao@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 5f88797..2503cef 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -200,6 +200,9 @@ static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
{
.compatible = "fsl,p1022-l2-cache-controller",
},
+ {
+ .compatible = "fsl,mpc8548-l2-cache-controller",
+ },
{},
};
--
1.6.4.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/9] powerpc/mpc8548cds: Add NOR flash node to dts
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
2012-03-06 9:06 ` [PATCH 3/9] l2sram: Add compatible entry for mpc8548 Zhao Chenhui
@ 2012-03-06 9:06 ` Zhao Chenhui
2012-03-16 20:22 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 5/9] powerpc/mpc8548cds: Add RapidIO " Zhao Chenhui
` (5 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Zhao Chenhui @ 2012-03-06 9:06 UTC (permalink / raw)
To: linuxppc-dev
From: chenhui zhao <chenhui.zhao@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/mpc8548cds.dts | 40 +++++++++++++++++++++++++++++++++-
1 files changed, 39 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 07b8dae..c3c8741 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,7 +1,7 @@
/*
* MPC8548 CDS Device Tree Source
*
- * Copyright 2006, 2008 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008, 2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -34,6 +34,44 @@
lbc: localbus@e0005000 {
reg = <0 0xe0005000 0 0x1000>;
+
+ ranges = <0x0 0x0 0x0 0xff000000 0x01000000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x01000000>;
+ bank-width = <2>;
+ device-width = <2>;
+
+ partition@0 {
+ reg = <0x0 0x0b00000>;
+ label = "ramdisk-nor";
+ };
+
+ partition@300000 {
+ reg = <0x0b00000 0x0400000>;
+ label = "kernel-nor";
+ };
+
+ partition@700000 {
+ reg = <0x0f00000 0x060000>;
+ label = "dtb-nor";
+ };
+
+ partition@760000 {
+ reg = <0x0f60000 0x020000>;
+ label = "env-nor";
+ read-only;
+ };
+
+ partition@780000 {
+ reg = <0x0f80000 0x080000>;
+ label = "u-boot-nor";
+ read-only;
+ };
+ };
};
soc: soc8548@e0000000 {
--
1.6.4.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 5/9] powerpc/mpc8548cds: Add RapidIO node to dts
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
2012-03-06 9:06 ` [PATCH 3/9] l2sram: Add compatible entry for mpc8548 Zhao Chenhui
2012-03-06 9:06 ` [PATCH 4/9] powerpc/mpc8548cds: Add NOR flash node to dts Zhao Chenhui
@ 2012-03-06 9:06 ` Zhao Chenhui
2012-03-16 20:23 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 6/9] powerpc/mpc8548cds: Add FPGA " Zhao Chenhui
` (4 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Zhao Chenhui @ 2012-03-06 9:06 UTC (permalink / raw)
To: linuxppc-dev
From: chenhui zhao <chenhui.zhao@freescale.com>
Enable RapidIO and add rapidio and rmu nodes to dts.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi | 16 ++++++++++++++++
arch/powerpc/boot/dts/mpc8548cds.dts | 7 +++++++
arch/powerpc/platforms/85xx/Kconfig | 1 +
3 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
index 9d8023a..579d76c 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -89,6 +89,21 @@
};
};
+&rio {
+ compatible = "fsl,srio";
+ interrupts = <48 2 0 0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ fsl,srio-rmu-handle = <&rmu>;
+ ranges;
+
+ port1 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <1>;
+ };
+};
+
&soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -134,6 +149,7 @@
/include/ "pq3-sec2.1-0.dtsi"
/include/ "pq3-mpic.dtsi"
+/include/ "pq3-rmu-0.dtsi"
global-utilities@e0000 {
compatible = "fsl,mpc8548-guts";
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index c3c8741..8d4df8e 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -339,6 +339,13 @@
0x0 0x100000>;
};
};
+
+ rio: rapidio@e00c0000 {
+ reg = <0x0 0xe00c0000 0x0 0x20000>;
+ port1 {
+ ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
+ };
+ };
};
/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d7946be..631dfd8 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -30,6 +30,7 @@ config MPC85xx_CDS
bool "Freescale MPC85xx CDS"
select DEFAULT_UIMAGE
select PPC_I8259
+ select HAS_RAPIDIO
help
This option enables support for the MPC85xx CDS board
--
1.6.4.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 6/9] powerpc/mpc8548cds: Add FPGA node to dts
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
` (2 preceding siblings ...)
2012-03-06 9:06 ` [PATCH 5/9] powerpc/mpc8548cds: Add RapidIO " Zhao Chenhui
@ 2012-03-06 9:06 ` Zhao Chenhui
2012-03-06 12:16 ` Kumar Gala
` (3 more replies)
2012-03-06 9:06 ` [PATCH 7/9] powerpc/mpc8548cds: fix alias in mpc8548si-pre.dtsi Zhao Chenhui
` (3 subsequent siblings)
7 siblings, 4 replies; 20+ messages in thread
From: Zhao Chenhui @ 2012-03-06 9:06 UTC (permalink / raw)
To: linuxppc-dev
From: chenhui zhao <chenhui.zhao@freescale.com>
Remove FPGA(CADMUS) macros in code. Move it to dts.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/mpc8548cds.dts | 8 ++++-
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 50 +++++++++++++++++++---------
2 files changed, 41 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 8d4df8e..0683983 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -35,7 +35,8 @@
lbc: localbus@e0005000 {
reg = <0 0xe0005000 0 0x1000>;
- ranges = <0x0 0x0 0x0 0xff000000 0x01000000>;
+ ranges = <0x0 0x0 0x0 0xff000000 0x01000000
+ 0x1 0x0 0x0 0xf8004000 0x00001000>;
nor@0,0 {
#address-cells = <1>;
@@ -72,6 +73,11 @@
read-only;
};
};
+
+ board-control@1,0 {
+ compatible = "fsl,mpc8548cds-fpga";
+ reg = <0x1 0x0 0x1000>;
+ };
};
soc: soc8548@e0000000 {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index c009c5b..a600dd0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -48,17 +48,24 @@
#include "mpc85xx.h"
-/* CADMUS info */
-/* xxx - galak, move into device tree */
-#define CADMUS_BASE (0xf8004000)
-#define CADMUS_SIZE (256)
-#define CM_VER (0)
-#define CM_CSR (1)
-#define CM_RST (2)
-
+/*
+ * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
+ * various logic and performs system control functions.
+ * Here is the FPGA/CPLD register map.
+ */
+struct cadmus_reg {
+ u8 cm_ver; /* Board version */
+ u8 cm_csr; /* General control/status */
+ u8 cm_rst; /* Reset control */
+ u8 cm_hsclk; /* High speed clock */
+ u8 cm_hsxclk; /* High speed clock extended */
+ u8 cm_led; /* LED data */
+ u8 cm_pci; /* PCI control/status */
+ u8 cm_dma; /* DMA control */
+ u8 res[248]; /* Total 256 bytes */
+};
-static int cds_pci_slot = 2;
-static volatile u8 *cadmus;
+static struct cadmus_reg *cadmus;
#ifdef CONFIG_PCI
@@ -274,20 +281,30 @@ machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
*/
static void __init mpc85xx_cds_setup_arch(void)
{
-#ifdef CONFIG_PCI
struct device_node *np;
-#endif
+ int cds_pci_slot;
if (ppc_md.progress)
ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
- cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
- cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
+ if (!np) {
+ pr_err("Could not find FPGA node.\n");
+ return;
+ }
+
+ cadmus = of_iomap(np, 0);
+ of_node_put(np);
+ if (!cadmus) {
+ pr_err("Fail to map FPGA area.\n");
+ return;
+ }
if (ppc_md.progress) {
char buf[40];
+ cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
- cadmus[CM_VER], cds_pci_slot);
+ in_8(&cadmus->cm_ver), cds_pci_slot);
ppc_md.progress(buf, 0);
}
@@ -317,7 +334,8 @@ static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
svid = mfspr(SPRN_SVR);
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
- seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
+ seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
+ in_8(&cadmus->cm_ver));
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
--
1.6.4.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 7/9] powerpc/mpc8548cds: fix alias in mpc8548si-pre.dtsi
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
` (3 preceding siblings ...)
2012-03-06 9:06 ` [PATCH 6/9] powerpc/mpc8548cds: Add FPGA " Zhao Chenhui
@ 2012-03-06 9:06 ` Zhao Chenhui
2012-03-16 20:23 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 8/9] powerpc/mpc8548cds: rename mpc8548cds.dts to mpc8548cds_32b.dts and create mpc8548cds.dtsi Zhao Chenhui
` (2 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Zhao Chenhui @ 2012-03-06 9:06 UTC (permalink / raw)
To: linuxppc-dev
Correct ethernet1 and add ethernet2 and ethernet3.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
index 289f121..720422d 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -43,7 +43,9 @@
serial0 = &serial0;
serial1 = &serial1;
ethernet0 = &enet0;
- ethernet1 = &enet2;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
--
1.6.4.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 8/9] powerpc/mpc8548cds: rename mpc8548cds.dts to mpc8548cds_32b.dts and create mpc8548cds.dtsi
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
` (4 preceding siblings ...)
2012-03-06 9:06 ` [PATCH 7/9] powerpc/mpc8548cds: fix alias in mpc8548si-pre.dtsi Zhao Chenhui
@ 2012-03-06 9:06 ` Zhao Chenhui
2012-03-16 20:23 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 9/9] powerpc/mpc8548cds: add 36-bit dts Zhao Chenhui
2012-03-06 12:15 ` [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Kumar Gala
7 siblings, 1 reply; 20+ messages in thread
From: Zhao Chenhui @ 2012-03-06 9:06 UTC (permalink / raw)
To: linuxppc-dev
* Create mpc8548cds.dtsi.
* Move lbc, soc and pci0 nodes to mpc8548cds_32b.dtsi.
* Change cuImage.mpc8548cds to cuImage.mpc8548cds_32b.
* Rename mpc8548cds.dts to mpc8548cds_32b.dts.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/boot/Makefile | 2 +-
arch/powerpc/boot/dts/mpc8548cds.dts | 357 ------------------------------
arch/powerpc/boot/dts/mpc8548cds.dtsi | 306 +++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8548cds_32b.dts | 86 +++++++
4 files changed, 393 insertions(+), 358 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/mpc8548cds.dts
create mode 100644 arch/powerpc/boot/dts/mpc8548cds.dtsi
create mode 100644 arch/powerpc/boot/dts/mpc8548cds_32b.dts
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 8844a17..f6622e0 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -247,7 +247,7 @@ image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads
image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \
- cuImage.mpc8548cds \
+ cuImage.mpc8548cds_32b \
cuImage.mpc8555cds
image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds
image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
deleted file mode 100644
index 0683983..0000000
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * MPC8548 CDS Device Tree Source
- *
- * Copyright 2006, 2008, 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-/include/ "fsl/mpc8548si-pre.dtsi"
-
-/ {
- model = "MPC8548CDS";
- compatible = "MPC8548CDS", "MPC85xxCDS";
-
- aliases {
- ethernet0 = &enet0;
- ethernet1 = &enet1;
- ethernet2 = &enet2;
- ethernet3 = &enet3;
- serial0 = &serial0;
- serial1 = &serial1;
- pci0 = &pci0;
- pci1 = &pci1;
- pci2 = &pci2;
- };
-
- memory {
- device_type = "memory";
- reg = <0 0 0x0 0x8000000>; // 128M at 0x0
- };
-
- lbc: localbus@e0005000 {
- reg = <0 0xe0005000 0 0x1000>;
-
- ranges = <0x0 0x0 0x0 0xff000000 0x01000000
- 0x1 0x0 0x0 0xf8004000 0x00001000>;
-
- nor@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash";
- reg = <0x0 0x0 0x01000000>;
- bank-width = <2>;
- device-width = <2>;
-
- partition@0 {
- reg = <0x0 0x0b00000>;
- label = "ramdisk-nor";
- };
-
- partition@300000 {
- reg = <0x0b00000 0x0400000>;
- label = "kernel-nor";
- };
-
- partition@700000 {
- reg = <0x0f00000 0x060000>;
- label = "dtb-nor";
- };
-
- partition@760000 {
- reg = <0x0f60000 0x020000>;
- label = "env-nor";
- read-only;
- };
-
- partition@780000 {
- reg = <0x0f80000 0x080000>;
- label = "u-boot-nor";
- read-only;
- };
- };
-
- board-control@1,0 {
- compatible = "fsl,mpc8548cds-fpga";
- reg = <0x1 0x0 0x1000>;
- };
- };
-
- soc: soc8548@e0000000 {
- ranges = <0 0x0 0xe0000000 0x100000>;
-
- i2c@3000 {
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- };
-
- eeprom@56 {
- compatible = "atmel,24c64";
- reg = <0x56>;
- };
-
- eeprom@57 {
- compatible = "atmel,24c64";
- reg = <0x57>;
- };
- };
-
- i2c@3100 {
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- };
- };
-
- enet0: ethernet@24000 {
- tbi-handle = <&tbi0>;
- phy-handle = <&phy0>;
- };
-
- mdio@24520 {
- phy0: ethernet-phy@0 {
- interrupts = <5 1 0 0>;
- reg = <0x0>;
- device_type = "ethernet-phy";
- };
- phy1: ethernet-phy@1 {
- interrupts = <5 1 0 0>;
- reg = <0x1>;
- device_type = "ethernet-phy";
- };
- phy2: ethernet-phy@2 {
- interrupts = <5 1 0 0>;
- reg = <0x2>;
- device_type = "ethernet-phy";
- };
- phy3: ethernet-phy@3 {
- interrupts = <5 1 0 0>;
- reg = <0x3>;
- device_type = "ethernet-phy";
- };
- tbi0: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
-
- enet1: ethernet@25000 {
- tbi-handle = <&tbi1>;
- phy-handle = <&phy1>;
- };
-
- mdio@25520 {
- tbi1: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
-
- enet2: ethernet@26000 {
- tbi-handle = <&tbi2>;
- phy-handle = <&phy2>;
- };
-
- mdio@26520 {
- tbi2: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
-
- enet3: ethernet@27000 {
- tbi-handle = <&tbi3>;
- phy-handle = <&phy3>;
- };
-
- mdio@27520 {
- tbi3: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
- };
-
- pci0: pci@e0008000 {
- reg = <0 0xe0008000 0 0x1000>;
- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
- 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
- clock-frequency = <66666666>;
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <
- /* IDSEL 0x4 (PCIX Slot 2) */
- 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
- 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
- /* IDSEL 0x5 (PCIX Slot 3) */
- 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
- 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
- 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
- 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
-
- /* IDSEL 0x6 (PCIX Slot 4) */
- 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
- 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
- 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
- 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
-
- /* IDSEL 0x8 (PCIX Slot 5) */
- 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
- 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
- /* IDSEL 0xC (Tsi310 bridge) */
- 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
- 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
- /* IDSEL 0x14 (Slot 2) */
- 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
- 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
- /* IDSEL 0x15 (Slot 3) */
- 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
- 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
- 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
- 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
-
- /* IDSEL 0x16 (Slot 4) */
- 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
- 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
- 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
- 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
-
- /* IDSEL 0x18 (Slot 5) */
- 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
- 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
- /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
- 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
- 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
-
- pci_bridge@1c {
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <
-
- /* IDSEL 0x00 (PrPMC Site) */
- 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
- 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
- /* IDSEL 0x04 (VIA chip) */
- 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
- 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
- /* IDSEL 0x05 (8139) */
- 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
-
- /* IDSEL 0x06 (Slot 6) */
- 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
- 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
- 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
- 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
-
- /* IDESL 0x07 (Slot 7) */
- 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
- 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
- 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
- 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
-
- reg = <0xe000 0x0 0x0 0x0 0x0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <0x2000000 0x0 0x80000000
- 0x2000000 0x0 0x80000000
- 0x0 0x20000000
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x80000>;
- clock-frequency = <33333333>;
-
- isa@4 {
- device_type = "isa";
- #interrupt-cells = <2>;
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <0x2000 0x0 0x0 0x0 0x0>;
- ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
- interrupt-parent = <&i8259>;
-
- i8259: interrupt-controller@20 {
- interrupt-controller;
- device_type = "interrupt-controller";
- reg = <0x1 0x20 0x2
- 0x1 0xa0 0x2
- 0x1 0x4d0 0x2>;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- compatible = "chrp,iic";
- interrupts = <0 1 0 0>;
- interrupt-parent = <&mpic>;
- };
-
- rtc@70 {
- compatible = "pnpPNP,b00";
- reg = <0x1 0x70 0x2>;
- };
- };
- };
- };
-
- pci1: pci@e0009000 {
- reg = <0 0xe0009000 0 0x1000>;
- ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
- 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
- clock-frequency = <66666666>;
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <
-
- /* IDSEL 0x15 */
- 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
- 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
- 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
- 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
- };
-
- pci2: pcie@e000a000 {
- reg = <0 0xe000a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
- 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
- pcie@0 {
- ranges = <0x2000000 0x0 0xa0000000
- 0x2000000 0x0 0xa0000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x100000>;
- };
- };
-
- rio: rapidio@e00c0000 {
- reg = <0x0 0xe00c0000 0x0 0x20000>;
- port1 {
- ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
- };
- };
-};
-
-/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dtsi b/arch/powerpc/boot/dts/mpc8548cds.dtsi
new file mode 100644
index 0000000..c61f525
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds.dtsi
@@ -0,0 +1,306 @@
+/*
+ * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&board_lbc {
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x01000000>;
+ bank-width = <2>;
+ device-width = <2>;
+
+ partition@0 {
+ reg = <0x0 0x0b00000>;
+ label = "ramdisk-nor";
+ };
+
+ partition@300000 {
+ reg = <0x0b00000 0x0400000>;
+ label = "kernel-nor";
+ };
+
+ partition@700000 {
+ reg = <0x0f00000 0x060000>;
+ label = "dtb-nor";
+ };
+
+ partition@760000 {
+ reg = <0x0f60000 0x020000>;
+ label = "env-nor";
+ read-only;
+ };
+
+ partition@780000 {
+ reg = <0x0f80000 0x080000>;
+ label = "u-boot-nor";
+ read-only;
+ };
+ };
+
+ board-control@1,0 {
+ compatible = "fsl,mpc8548cds-fpga";
+ reg = <0x1 0x0 0x1000>;
+ };
+};
+
+&board_soc {
+ i2c@3000 {
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+ };
+
+ i2c@3100 {
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+
+ enet0: ethernet@24000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ };
+
+ mdio@24520 {
+ phy0: ethernet-phy@0 {
+ interrupts = <5 1 0 0>;
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy@1 {
+ interrupts = <5 1 0 0>;
+ reg = <0x1>;
+ device_type = "ethernet-phy";
+ };
+ phy2: ethernet-phy@2 {
+ interrupts = <5 1 0 0>;
+ reg = <0x2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupts = <5 1 0 0>;
+ reg = <0x3>;
+ device_type = "ethernet-phy";
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet1: ethernet@25000 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ };
+
+ mdio@25520 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet2: ethernet@26000 {
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy2>;
+ };
+
+ mdio@26520 {
+ tbi2: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet3: ethernet@27000 {
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy3>;
+ };
+
+ mdio@27520 {
+ tbi3: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+};
+
+&board_pci0 {
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x4 (PCIX Slot 2) */
+ 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+ 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+ /* IDSEL 0x5 (PCIX Slot 3) */
+ 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
+ 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
+ 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
+ 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
+
+ /* IDSEL 0x6 (PCIX Slot 4) */
+ 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+ 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+ 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
+ 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+
+ /* IDSEL 0x8 (PCIX Slot 5) */
+ 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+ 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+ /* IDSEL 0xC (Tsi310 bridge) */
+ 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+ 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+ /* IDSEL 0x14 (Slot 2) */
+ 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+ 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+ /* IDSEL 0x15 (Slot 3) */
+ 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
+ 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
+ 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
+ 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
+
+ /* IDSEL 0x16 (Slot 4) */
+ 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+ 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+ 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
+ 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+
+ /* IDSEL 0x18 (Slot 5) */
+ 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+ 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+ /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+ 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+ 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
+
+ pci_bridge@1c {
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ /* IDSEL 0x00 (PrPMC Site) */
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+ /* IDSEL 0x04 (VIA chip) */
+ 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+ 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+ /* IDSEL 0x05 (8139) */
+ 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
+
+ /* IDSEL 0x06 (Slot 6) */
+ 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+ 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+ 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
+ 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+
+ /* IDESL 0x07 (Slot 7) */
+ 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+ 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
+ 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+ 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
+
+ reg = <0xe000 0x0 0x0 0x0 0x0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x80000>;
+ clock-frequency = <33333333>;
+
+ isa@4 {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <0x2000 0x0 0x0 0x0 0x0>;
+ ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <0x1 0x20 0x2
+ 0x1 0xa0 0x2
+ 0x1 0x4d0 0x2>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <0 1 0 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <0x1 0x70 0x2>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8548cds_32b.dts b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
new file mode 100644
index 0000000..6fd6316
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
@@ -0,0 +1,86 @@
+/*
+ * MPC8548 CDS Device Tree Source (32-bit address map)
+ *
+ * Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/mpc8548si-pre.dtsi"
+
+/ {
+ model = "MPC8548CDS";
+ compatible = "MPC8548CDS", "MPC85xxCDS";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0x0 0x8000000>; // 128M at 0x0
+ };
+
+ board_lbc: lbc: localbus@e0005000 {
+ reg = <0 0xe0005000 0 0x1000>;
+
+ ranges = <0x0 0x0 0x0 0xff000000 0x01000000
+ 0x1 0x0 0x0 0xf8004000 0x00001000>;
+
+ };
+
+ board_soc: soc: soc8548@e0000000 {
+ ranges = <0 0x0 0xe0000000 0x100000>;
+ };
+
+ board_pci0: pci0: pci@e0008000 {
+ reg = <0 0xe0008000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
+ clock-frequency = <66666666>;
+ };
+
+ pci1: pci@e0009000 {
+ reg = <0 0xe0009000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
+ clock-frequency = <66666666>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
+ 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
+ };
+
+ pci2: pcie@e000a000 {
+ reg = <0 0xe000a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ rio: rapidio@e00c0000 {
+ reg = <0x0 0xe00c0000 0x0 0x20000>;
+ port1 {
+ ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
+ };
+ };
+};
+
+/*
+ * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
+ * for interrupt-map & interrupt-map-mask.
+ */
+
+/include/ "fsl/mpc8548si-post.dtsi"
+/include/ "mpc8548cds.dtsi"
--
1.6.4.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 9/9] powerpc/mpc8548cds: add 36-bit dts
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
` (5 preceding siblings ...)
2012-03-06 9:06 ` [PATCH 8/9] powerpc/mpc8548cds: rename mpc8548cds.dts to mpc8548cds_32b.dts and create mpc8548cds.dtsi Zhao Chenhui
@ 2012-03-06 9:06 ` Zhao Chenhui
2012-03-16 20:23 ` Kumar Gala
2012-03-06 12:15 ` [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Kumar Gala
7 siblings, 1 reply; 20+ messages in thread
From: Zhao Chenhui @ 2012-03-06 9:06 UTC (permalink / raw)
To: linuxppc-dev
Create mpc8548cds_36b.dts. Support 36-bit mode.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/mpc8548cds_36b.dts | 86 ++++++++++++++++++++++++++++++
1 files changed, 86 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8548cds_36b.dts
diff --git a/arch/powerpc/boot/dts/mpc8548cds_36b.dts b/arch/powerpc/boot/dts/mpc8548cds_36b.dts
new file mode 100644
index 0000000..10e551b
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_36b.dts
@@ -0,0 +1,86 @@
+/*
+ * MPC8548 CDS Device Tree Source (36-bit address map)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/mpc8548si-pre.dtsi"
+
+/ {
+ model = "MPC8548CDS";
+ compatible = "MPC8548CDS", "MPC85xxCDS";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0x0 0x8000000>; // 128M at 0x0
+ };
+
+ board_lbc: lbc: localbus@fe0005000 {
+ reg = <0xf 0xe0005000 0 0x1000>;
+
+ ranges = <0x0 0x0 0xf 0xff000000 0x01000000
+ 0x1 0x0 0xf 0xf8004000 0x00001000>;
+
+ };
+
+ board_soc: soc: soc8548@fe0000000 {
+ ranges = <0 0xf 0xe0000000 0x100000>;
+ };
+
+ board_pci0: pci0: pci@fe0008000 {
+ reg = <0xf 0xe0008000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
+ clock-frequency = <66666666>;
+ };
+
+ pci1: pci@fe0009000 {
+ reg = <0xf 0xe0009000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>;
+ clock-frequency = <66666666>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
+ 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+ 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+ 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
+ };
+
+ pci2: pcie@fe000a000 {
+ reg = <0xf 0xe000a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x100000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ rio: rapidio@fe00c0000 {
+ reg = <0xf 0xe00c0000 0x0 0x20000>;
+ port1 {
+ ranges = <0x0 0x0 0xc 0x40000000 0x0 0x20000000>;
+ };
+ };
+};
+
+/*
+ * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
+ * for interrupt-map & interrupt-map-mask.
+ */
+
+/include/ "fsl/mpc8548si-post.dtsi"
+/include/ "mpc8548cds.dtsi"
--
1.6.4.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
` (6 preceding siblings ...)
2012-03-06 9:06 ` [PATCH 9/9] powerpc/mpc8548cds: add 36-bit dts Zhao Chenhui
@ 2012-03-06 12:15 ` Kumar Gala
2012-03-07 9:31 ` Zhao Chenhui-B35336
7 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2012-03-06 12:15 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
>=20
> There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
> southbridge chip.
>=20
> The bootloader sets the PCI bridge to open a window from 0x0000
> to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
> resource. In the routine pci_read_bridge_io(), if the base which
> is read from PCI_IO_BASE is equal to zero, the routine don't set
> the I/O resource of the child bus.
>=20
> To allow the legacy I/O space on the VIA southbridge to be accessed,
> use the fixup to fix the PCI I/O space of the PCI bridge.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/platforms/85xx/mpc85xx_cds.c | 29 =
+++++++++++++++++++++++++++--
> 1 files changed, 27 insertions(+), 2 deletions(-)
>=20
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c =
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> index 40f03da..c009c5b 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> @@ -3,7 +3,7 @@
> *
> * Maintained by Kumar Gala (see MAINTAINERS for contact information)
> *
> - * Copyright 2005 Freescale Semiconductor Inc.
> + * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
> *
> * This program is free software; you can redistribute it and/or =
modify it
> * under the terms of the GNU General Public License as published =
by the
> @@ -158,6 +158,31 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, =
skip_fake_bridge);
> DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
> DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
>=20
> +/*
> + * Fix Tsi310 PCI-X bridge resource.
> + * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O =
space.
> + * This allows legacy I/O(i8259, etc) on the VIA southbridge to be =
accessed.
> + */
This comment and the code don't make sense. Why is the bridge described =
as Tsi310 in comments but the vendor ID is IBM ?
> +void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
> +{
> + struct pci_dev *dev =3D bus->self;
> + struct resource *res =3D bus->resource[0];
> +
> + if (dev !=3D NULL &&
> + dev->vendor =3D=3D PCI_VENDOR_ID_IBM &&
> + dev->device =3D=3D PCI_DEVICE_ID_IBM_PCIX_BRIDGE) {
> + if (res) {
> + res->start =3D 0;
> + res->end =3D 0x1fff;
> + res->flags =3D IORESOURCE_IO;
> + pr_info("mpc85xx_cds: PCI bridge resource fixup =
applied\n");
> + pr_info("mpc85xx_cds: %pR\n", res);
> + }
> + }
> +
> + fsl_pcibios_fixup_bus(bus);
> +}
> +
> #ifdef CONFIG_PPC_I8259
> static void mpc85xx_8259_cascade_handler(unsigned int irq,
> struct irq_desc *desc)
> @@ -323,7 +348,7 @@ define_machine(mpc85xx_cds) {
> .get_irq =3D mpic_get_irq,
> #ifdef CONFIG_PCI
> .restart =3D mpc85xx_cds_restart,
> - .pcibios_fixup_bus =3D fsl_pcibios_fixup_bus,
> + .pcibios_fixup_bus =3D mpc85xx_cds_fixup_bus,
> #else
> .restart =3D fsl_rstcr_restart,
> #endif
> --=20
> 1.6.4.1
>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 6/9] powerpc/mpc8548cds: Add FPGA node to dts
2012-03-06 9:06 ` [PATCH 6/9] powerpc/mpc8548cds: Add FPGA " Zhao Chenhui
@ 2012-03-06 12:16 ` Kumar Gala
2012-03-07 16:22 ` Tabi Timur-B04825
` (2 subsequent siblings)
3 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2012-03-06 12:16 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev@lists.ozlabs.org list, Zhao Chenhui
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
>=20
> Remove FPGA(CADMUS) macros in code. Move it to dts.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
Timur,
Do you mind reviewing & ack'ing.
- k
> arch/powerpc/boot/dts/mpc8548cds.dts | 8 ++++-
> arch/powerpc/platforms/85xx/mpc85xx_cds.c | 50 =
+++++++++++++++++++---------
> 2 files changed, 41 insertions(+), 17 deletions(-)
>=20
> diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts =
b/arch/powerpc/boot/dts/mpc8548cds.dts
> index 8d4df8e..0683983 100644
> --- a/arch/powerpc/boot/dts/mpc8548cds.dts
> +++ b/arch/powerpc/boot/dts/mpc8548cds.dts
> @@ -35,7 +35,8 @@
> lbc: localbus@e0005000 {
> reg =3D <0 0xe0005000 0 0x1000>;
>=20
> - ranges =3D <0x0 0x0 0x0 0xff000000 0x01000000>;
> + ranges =3D <0x0 0x0 0x0 0xff000000 0x01000000
> + 0x1 0x0 0x0 0xf8004000 0x00001000>;
>=20
> nor@0,0 {
> #address-cells =3D <1>;
> @@ -72,6 +73,11 @@
> read-only;
> };
> };
> +
> + board-control@1,0 {
> + compatible =3D "fsl,mpc8548cds-fpga";
> + reg =3D <0x1 0x0 0x1000>;
> + };
> };
>=20
> soc: soc8548@e0000000 {
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c =
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> index c009c5b..a600dd0 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> @@ -48,17 +48,24 @@
>=20
> #include "mpc85xx.h"
>=20
> -/* CADMUS info */
> -/* xxx - galak, move into device tree */
> -#define CADMUS_BASE (0xf8004000)
> -#define CADMUS_SIZE (256)
> -#define CM_VER (0)
> -#define CM_CSR (1)
> -#define CM_RST (2)
> -
> +/*
> + * The CDS board contains an FPGA/CPLD called "Cadmus", which =
collects
> + * various logic and performs system control functions.
> + * Here is the FPGA/CPLD register map.
> + */
> +struct cadmus_reg {
> + u8 cm_ver; /* Board version */
> + u8 cm_csr; /* General control/status */
> + u8 cm_rst; /* Reset control */
> + u8 cm_hsclk; /* High speed clock */
> + u8 cm_hsxclk; /* High speed clock extended */
> + u8 cm_led; /* LED data */
> + u8 cm_pci; /* PCI control/status */
> + u8 cm_dma; /* DMA control */
> + u8 res[248]; /* Total 256 bytes */
> +};
>=20
> -static int cds_pci_slot =3D 2;
> -static volatile u8 *cadmus;
> +static struct cadmus_reg *cadmus;
>=20
> #ifdef CONFIG_PCI
>=20
> @@ -274,20 +281,30 @@ machine_device_initcall(mpc85xx_cds, =
mpc85xx_cds_8259_attach);
> */
> static void __init mpc85xx_cds_setup_arch(void)
> {
> -#ifdef CONFIG_PCI
> struct device_node *np;
> -#endif
> + int cds_pci_slot;
>=20
> if (ppc_md.progress)
> ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
>=20
> - cadmus =3D ioremap(CADMUS_BASE, CADMUS_SIZE);
> - cds_pci_slot =3D ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
> + np =3D of_find_compatible_node(NULL, NULL, =
"fsl,mpc8548cds-fpga");
> + if (!np) {
> + pr_err("Could not find FPGA node.\n");
> + return;
> + }
> +
> + cadmus =3D of_iomap(np, 0);
> + of_node_put(np);
> + if (!cadmus) {
> + pr_err("Fail to map FPGA area.\n");
> + return;
> + }
>=20
> if (ppc_md.progress) {
> char buf[40];
> + cds_pci_slot =3D ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + =
1;
> snprintf(buf, 40, "CDS Version =3D 0x%x in slot %d\n",
> - cadmus[CM_VER], cds_pci_slot);
> + in_8(&cadmus->cm_ver), cds_pci_slot);
> ppc_md.progress(buf, 0);
> }
>=20
> @@ -317,7 +334,8 @@ static void mpc85xx_cds_show_cpuinfo(struct =
seq_file *m)
> svid =3D mfspr(SPRN_SVR);
>=20
> seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
> - seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", =
cadmus[CM_VER]);
> + seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
> + in_8(&cadmus->cm_ver));
> seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
> seq_printf(m, "SVR\t\t: 0x%x\n", svid);
>=20
> --=20
> 1.6.4.1
>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge
2012-03-06 12:15 ` [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Kumar Gala
@ 2012-03-07 9:31 ` Zhao Chenhui-B35336
2012-03-07 10:45 ` Kumar Gala
0 siblings, 1 reply; 20+ messages in thread
From: Zhao Chenhui-B35336 @ 2012-03-07 9:31 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev@lists.ozlabs.org, Li Yang-R58472
> > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/p=
latforms/85xx/mpc85xx_cds.c
> > index 40f03da..c009c5b 100644
> > --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> > +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> > @@ -3,7 +3,7 @@
> > *
> > * Maintained by Kumar Gala (see MAINTAINERS for contact information)
> > *
> > - * Copyright 2005 Freescale Semiconductor Inc.
> > + * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
> > *
> > * This program is free software; you can redistribute it and/or modif=
y it
> > * under the terms of the GNU General Public License as published by=
the
> > @@ -158,6 +158,31 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_=
bridge);
> > DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
> > DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
> >
> > +/*
> > + * Fix Tsi310 PCI-X bridge resource.
> > + * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O spa=
ce.
> > + * This allows legacy I/O(i8259, etc) on the VIA southbridge to be acc=
essed.
> > + */
>=20
> This comment and the code don't make sense. Why is the bridge described =
as Tsi310 in comments but the
> vendor ID is IBM ?
This chip is from IBM originally, and bought by IDT.
The vendor ID is IBM, but the part number is Tsi310(IDT).
-Chenhui
>=20
> > +void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
> > +{
> > + struct pci_dev *dev =3D bus->self;
> > + struct resource *res =3D bus->resource[0];
> > +
> > + if (dev !=3D NULL &&
> > + dev->vendor =3D=3D PCI_VENDOR_ID_IBM &&
> > + dev->device =3D=3D PCI_DEVICE_ID_IBM_PCIX_BRIDGE) {
> > + if (res) {
> > + res->start =3D 0;
> > + res->end =3D 0x1fff;
> > + res->flags =3D IORESOURCE_IO;
> > + pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
> > + pr_info("mpc85xx_cds: %pR\n", res);
> > + }
> > + }
> > +
> > + fsl_pcibios_fixup_bus(bus);
> > +}
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge
2012-03-07 9:31 ` Zhao Chenhui-B35336
@ 2012-03-07 10:45 ` Kumar Gala
0 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2012-03-07 10:45 UTC (permalink / raw)
To: Zhao Chenhui-B35336; +Cc: linuxppc-dev@lists.ozlabs.org, Li Yang-R58472
On Mar 7, 2012, at 3:31 AM, Zhao Chenhui-B35336 wrote:
>>> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c =
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
>>> index 40f03da..c009c5b 100644
>>> --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
>>> +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
>>> @@ -3,7 +3,7 @@
>>> *
>>> * Maintained by Kumar Gala (see MAINTAINERS for contact information)
>>> *
>>> - * Copyright 2005 Freescale Semiconductor Inc.
>>> + * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
>>> *
>>> * This program is free software; you can redistribute it and/or =
modify it
>>> * under the terms of the GNU General Public License as published =
by the
>>> @@ -158,6 +158,31 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, =
skip_fake_bridge);
>>> DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
>>> DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
>>>=20
>>> +/*
>>> + * Fix Tsi310 PCI-X bridge resource.
>>> + * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O =
space.
>>> + * This allows legacy I/O(i8259, etc) on the VIA southbridge to be =
accessed.
>>> + */
>>=20
>> This comment and the code don't make sense. Why is the bridge =
described as Tsi310 in comments but the
>> vendor ID is IBM ?
>=20
> This chip is from IBM originally, and bought by IDT.
> The vendor ID is IBM, but the part number is Tsi310(IDT).
>=20
Ok, we should probably call it PCI_DEVICE_ID_..._TSI310
- k
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 6/9] powerpc/mpc8548cds: Add FPGA node to dts
2012-03-06 9:06 ` [PATCH 6/9] powerpc/mpc8548cds: Add FPGA " Zhao Chenhui
2012-03-06 12:16 ` Kumar Gala
@ 2012-03-07 16:22 ` Tabi Timur-B04825
2012-03-07 16:24 ` Timur Tabi
2012-03-16 20:22 ` Kumar Gala
3 siblings, 0 replies; 20+ messages in thread
From: Tabi Timur-B04825 @ 2012-03-07 16:22 UTC (permalink / raw)
To: Zhao Chenhui-B35336; +Cc: linuxppc-dev@lists.ozlabs.org
On Tue, Mar 6, 2012 at 3:06 AM, Zhao Chenhui <chenhui.zhao@freescale.com> w=
rote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
>
> Remove FPGA(CADMUS) macros in code. Move it to dts.
>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
Acked-by: Timur Tabi <timur@freescale.com>
--=20
Timur Tabi
Linux kernel developer at Freescale=
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 6/9] powerpc/mpc8548cds: Add FPGA node to dts
2012-03-06 9:06 ` [PATCH 6/9] powerpc/mpc8548cds: Add FPGA " Zhao Chenhui
2012-03-06 12:16 ` Kumar Gala
2012-03-07 16:22 ` Tabi Timur-B04825
@ 2012-03-07 16:24 ` Timur Tabi
2012-03-16 20:22 ` Kumar Gala
3 siblings, 0 replies; 20+ messages in thread
From: Timur Tabi @ 2012-03-07 16:24 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
On Tue, Mar 6, 2012 at 3:06 AM, Zhao Chenhui <chenhui.zhao@freescale.com>
wrote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
>
> Remove FPGA(CADMUS) macros in code. Move it to dts.
>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
Acked-by: Timur Tabi <timur@freescale.com>
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 6/9] powerpc/mpc8548cds: Add FPGA node to dts
2012-03-06 9:06 ` [PATCH 6/9] powerpc/mpc8548cds: Add FPGA " Zhao Chenhui
` (2 preceding siblings ...)
2012-03-07 16:24 ` Timur Tabi
@ 2012-03-16 20:22 ` Kumar Gala
3 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2012-03-16 20:22 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
>=20
> Remove FPGA(CADMUS) macros in code. Move it to dts.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/boot/dts/mpc8548cds.dts | 8 ++++-
> arch/powerpc/platforms/85xx/mpc85xx_cds.c | 50 =
+++++++++++++++++++---------
> 2 files changed, 41 insertions(+), 17 deletions(-)
applied
- k=
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/9] powerpc/mpc8548cds: Add NOR flash node to dts
2012-03-06 9:06 ` [PATCH 4/9] powerpc/mpc8548cds: Add NOR flash node to dts Zhao Chenhui
@ 2012-03-16 20:22 ` Kumar Gala
0 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2012-03-16 20:22 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/boot/dts/mpc8548cds.dts | 40 =
+++++++++++++++++++++++++++++++++-
> 1 files changed, 39 insertions(+), 1 deletions(-)
applied
- k=
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/9] powerpc/mpc8548cds: Add RapidIO node to dts
2012-03-06 9:06 ` [PATCH 5/9] powerpc/mpc8548cds: Add RapidIO " Zhao Chenhui
@ 2012-03-16 20:23 ` Kumar Gala
0 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2012-03-16 20:23 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
>
> Enable RapidIO and add rapidio and rmu nodes to dts.
>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi | 16 ++++++++++++++++
> arch/powerpc/boot/dts/mpc8548cds.dts | 7 +++++++
> arch/powerpc/platforms/85xx/Kconfig | 1 +
> 3 files changed, 24 insertions(+), 0 deletions(-)
applied
- k
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] powerpc/mpc8548cds: fix alias in mpc8548si-pre.dtsi
2012-03-06 9:06 ` [PATCH 7/9] powerpc/mpc8548cds: fix alias in mpc8548si-pre.dtsi Zhao Chenhui
@ 2012-03-16 20:23 ` Kumar Gala
0 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2012-03-16 20:23 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> Correct ethernet1 and add ethernet2 and ethernet3.
>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
applied
- k
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 8/9] powerpc/mpc8548cds: rename mpc8548cds.dts to mpc8548cds_32b.dts and create mpc8548cds.dtsi
2012-03-06 9:06 ` [PATCH 8/9] powerpc/mpc8548cds: rename mpc8548cds.dts to mpc8548cds_32b.dts and create mpc8548cds.dtsi Zhao Chenhui
@ 2012-03-16 20:23 ` Kumar Gala
0 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2012-03-16 20:23 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> * Create mpc8548cds.dtsi.
> * Move lbc, soc and pci0 nodes to mpc8548cds_32b.dtsi.
> * Change cuImage.mpc8548cds to cuImage.mpc8548cds_32b.
> * Rename mpc8548cds.dts to mpc8548cds_32b.dts.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/boot/Makefile | 2 +-
> arch/powerpc/boot/dts/mpc8548cds.dts | 357 =
------------------------------
> arch/powerpc/boot/dts/mpc8548cds.dtsi | 306 =
+++++++++++++++++++++++++
> arch/powerpc/boot/dts/mpc8548cds_32b.dts | 86 +++++++
> 4 files changed, 393 insertions(+), 358 deletions(-)
> delete mode 100644 arch/powerpc/boot/dts/mpc8548cds.dts
> create mode 100644 arch/powerpc/boot/dts/mpc8548cds.dtsi
> create mode 100644 arch/powerpc/boot/dts/mpc8548cds_32b.dts
applied
- k=
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 9/9] powerpc/mpc8548cds: add 36-bit dts
2012-03-06 9:06 ` [PATCH 9/9] powerpc/mpc8548cds: add 36-bit dts Zhao Chenhui
@ 2012-03-16 20:23 ` Kumar Gala
0 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2012-03-16 20:23 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> Create mpc8548cds_36b.dts. Support 36-bit mode.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/boot/dts/mpc8548cds_36b.dts | 86 =
++++++++++++++++++++++++++++++
> 1 files changed, 86 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/mpc8548cds_36b.dts
applied
- k=
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2012-03-16 20:23 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-03-06 9:06 [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Zhao Chenhui
2012-03-06 9:06 ` [PATCH 3/9] l2sram: Add compatible entry for mpc8548 Zhao Chenhui
2012-03-06 9:06 ` [PATCH 4/9] powerpc/mpc8548cds: Add NOR flash node to dts Zhao Chenhui
2012-03-16 20:22 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 5/9] powerpc/mpc8548cds: Add RapidIO " Zhao Chenhui
2012-03-16 20:23 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 6/9] powerpc/mpc8548cds: Add FPGA " Zhao Chenhui
2012-03-06 12:16 ` Kumar Gala
2012-03-07 16:22 ` Tabi Timur-B04825
2012-03-07 16:24 ` Timur Tabi
2012-03-16 20:22 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 7/9] powerpc/mpc8548cds: fix alias in mpc8548si-pre.dtsi Zhao Chenhui
2012-03-16 20:23 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 8/9] powerpc/mpc8548cds: rename mpc8548cds.dts to mpc8548cds_32b.dts and create mpc8548cds.dtsi Zhao Chenhui
2012-03-16 20:23 ` Kumar Gala
2012-03-06 9:06 ` [PATCH 9/9] powerpc/mpc8548cds: add 36-bit dts Zhao Chenhui
2012-03-16 20:23 ` Kumar Gala
2012-03-06 12:15 ` [PATCH 2/9] powerpc/mpc85xxcds: Fix PCI I/O space resource of PCI bridge Kumar Gala
2012-03-07 9:31 ` Zhao Chenhui-B35336
2012-03-07 10:45 ` Kumar Gala
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