From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id B2971DDFB2 for ; Wed, 30 May 2007 22:13:45 +1000 (EST) In-Reply-To: <20070530100438.GB24586@lst.de> References: <40815D64-3AD7-49C6-9A58-C7848691D940@kernel.crashing.org> <77D9DB04-FAD3-48EF-9159-5EA92BB366E5@freescale.com> <20070530100438.GB24586@lst.de> Mime-Version: 1.0 (Apple Message framework v752.2) Content-Type: text/plain; charset=US-ASCII; delsp=yes; format=flowed Message-Id: From: Kumar Gala Subject: Re: Saving to 32 bits of GPRs in signal context Date: Wed, 30 May 2007 07:13:26 -0500 To: Christoph Hellwig Cc: linuxppc-dev list , Steve Munroe , Ulrich Weigand , Paul Mackerras , Anton Blanchard List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On May 30, 2007, at 5:04 AM, Christoph Hellwig wrote: > On Tue, May 29, 2007 at 02:04:02PM -0500, Becky Bruce wrote: >> I think that's exactly what Kumar's talking about. The assumption >> that all 64-bit Power processors will use those upper bits in some >> meaningful way is not valid. Also, ld and std do not architecturally >> "just work" on BookE implementations running in 32b mode. Those >> instructions are part of the 64-bit category in 2.03, and may illop >> on BookE processors running in 32b mode. > > Then Bens suggest mode will only work on the sane IBM processors and > not the braindead freescale ones. Wouldn't be the first time. This isn't sane vs braindead. Its one thing if this was some quirk of an implementation, but we are talking about what the architecture does and doesn't allow. There a reasonable reason that a processor for the embedded processor would be able to save power in 32-bit mode by not powering the upper bits of the register file. - k