From: Eric Van Hensbergen <ericvh@gmail.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
bg-linux@lists.anl-external.org
Subject: Re: [PATCH] [RFC][V3] bluegene: use MMU feature flag to conditionalize L1 writethrough code
Date: Thu, 9 Jun 2011 22:23:20 -0500 [thread overview]
Message-ID: <BANLkTikRYDH3K1wOdMzzvVP--frRezVnRQ@mail.gmail.com> (raw)
In-Reply-To: <1307662948.2874.293.camel@pasglop>
On Thu, Jun 9, 2011 at 6:42 PM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Thu, 2011-06-09 at 09:58 -0500, Eric Van Hensbergen wrote:
>> On Tue, Jun 7, 2011 at 7:47 PM, Benjamin Herrenschmidt
>> <benh@kernel.crashing.org> wrote:
>> > BTW. Care to explain to me why you have U2 -both- in the arguments to
>> > tlbwe and in MMUCR ? That doesn't look right to me... which one is used
>> > where and when ?
>> >
>>
>> My reading of the databook is that U2SWOAE is an enable bit that lets the U2
>> storage attribute control the behavior.
>
> You mean the MMUCR variant ?
>
Yeah, the MMCR variant acts as an enable/mask for the U2 storage attribute.
>
> Well, point is, parsing the device-tree from early boot asm is nasty,
> unless you start extending the header but that sucks. That's why I'm
> thinking it might be a good idea to look at what it takes to "convert"
> the initial entry instead, even if that involves some cache flushing
> (provided that's workable at all of course).
>
ah, okay. I guess if its happening before the secondary cpus come up
then that should be workable. I guess it doesn't hurt to try.
-eric
prev parent reply other threads:[~2011-06-10 3:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-07 21:36 [PATCH] [RFC][V3] bluegene: use MMU feature flag to conditionalize L1 writethrough code Eric Van Hensbergen
2011-06-08 0:47 ` Benjamin Herrenschmidt
2011-06-09 14:58 ` Eric Van Hensbergen
2011-06-09 23:42 ` Benjamin Herrenschmidt
2011-06-10 3:23 ` Eric Van Hensbergen [this message]
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