From: "dabby bentam" <db260179@hotmail.com>
To: linuxppc-dev@ozlabs.org
Subject: [AGPGART] Attempting to create a agpgart driver for ArticiaS, help appreciated!
Date: Wed, 04 Jan 2006 10:51:58 +0000 [thread overview]
Message-ID: <BAY102-F95E7B86A73B08AF3E5FFBC22F0@phx.gbl> (raw)
[-- Attachment #1: Type: text/plain, Size: 819 bytes --]
This is a long shot.
Between me and geri pircher we are trying to get the agpgart driver working
for the pegasos 1 and amigaone boards (using the ArticiaS northbridge
http://www.mai.com).
Find the attached source file (articias-agp.c), You might need to remove the
debug code.
So far, the aperture size works and is detected as 204m, but the gatt table
cannot allocate any memory - complains that ioremap is using memory from
RAM.
The ArticiaS masks its bridge memory (i'm sure the uninorth does the same?).
Is there anyway to find out the mask memory, or is the code completly wrong?
This source code should work on 2.6 kernel.
Thanks for any help or guidence in advance.
PegXlin Developer
Pegxmac, Pegxlin
Versatile LIVE CD's for Pegasos Mainboards
http://pegxmac.zftp.com
http://www.pegasosppc.com
[-- Attachment #2: articias-agp.c --]
[-- Type: application/octet-stream, Size: 27262 bytes --]
/*
* ArticiaS AGPGART routines.
*/
#include <linux/types.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include "agp.h"
static struct pci_device_id agp_articias_pci_table[];
#define ARTICIAS_DEBUG
#define ARTICIAS_AGP_EN 0x49 /* bit 0 -> AGP enable */
#define ARTICIAS_GART_EN 0x58 /* bit 6 -> GART enable */
#define ARTICIAS_APSIZE 0x59 /* bits 2:0 set size */
#define ARTICIAS_APBASE 0x59 /* TLB address Base [31:12]*/
#define ARTICIAS_GATTBASE 0x10 /* GART base address register */
#define ARTICIAS_TLB_BASE 0x5A /* bits 16:31 of TLB base address */
#define ARTICIAS_GATT_MASK 0xFFFFF000 /* Geri: new mask. */
#define ARTICIAS_SIZE_MASK 0x07 /* Mask aperture size bits. */
#define ARTICIAP_SIZE_MASK 0x0F /* not yet used - vaporware IC. */
/* Original code from MAI. */
// #define ARTICIAS_GATTBASE 0x12 /* GART base address register */
// #define ARTICIAS_GATT_MASK 0xF0000000 /* MAI says fix me! */
static int articias_fetch_size(void)
{
int i;
u8 temp;
struct aper_size_info_8 *values;
values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
pci_read_config_byte(agp_bridge->dev, ARTICIAS_APSIZE, &temp);
#ifdef ARTICIAS_DEBUG
printk(KERN_INFO PFX "[ARTICIAS] articias_fetch_size()\n");
printk(KERN_INFO PFX "[ARTICIAS] * non masked temp = 0x%x\n", temp);
#endif
/* Mask the GART/Aperture size selection bits. */
temp = temp & ARTICIAS_SIZE_MASK;
for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
#ifdef ARTICIAS_DEBUG
void *temp2;
printk(KERN_INFO PFX "[ARTICIAS] * aperature size loop index #%d\n", i);
printk(KERN_INFO PFX "[ARTICIAS] * values[%d].size_value = %x\n", i, (u32) values[i].size_value);
#endif
if (temp == values[i].size_value) {
agp_bridge->previous_size =
agp_bridge->current_size = (void *) (values + i);
/* Geri: Was <(void *) (values)> before, but that
* didn't make sense to me!? Otherwise it would always
* point to the same value!
*/
agp_bridge->aperture_size_idx = i;
#ifdef ARTICIAS_DEBUG
temp2 = agp_bridge->current_size;
printk(KERN_INFO PFX "[ARTICIAS] * masked temp = 0x%x\n", temp);
printk(KERN_INFO PFX "[ARTICIAS] * values[%d].size = %d\n", i, values[i].size);
printk(KERN_INFO PFX "[ARTICIAS] * current_size->size = %d\n", A_SIZE_8(temp2)->size);
printk(KERN_INFO PFX "[ARTICIAS] * current_size->page_order = %d\n", A_SIZE_8(temp2)->page_order);
printk(KERN_INFO PFX "[ARTICIAS] * current_size->num_entries = %d\n", A_SIZE_8(temp2)->num_entries);
printk(KERN_INFO PFX "[ARTICIAS] * current_size->size_value = %d\n", A_SIZE_8(temp2)->size_value);
#endif
return values[i].size;
}
}
printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
return 0;
}
static int articias_configure(void)
{
u32 temp = 0;
u16 shift = 0;
struct aper_size_info_8 *current_size;
#ifdef ARTICIAS_DEBUG
printk(KERN_INFO PFX "[ARTICIAS] articias_configure()\n");
#endif
/* Get current aperture size */
current_size = A_SIZE_8(agp_bridge->current_size);
temp = (u32) agp_bridge->gatt_table_real;
/* Get upper word from dword. Note that the ArticiaS should have 20
* bits for the TLB base address. Otherwise the PCI write config code
* for the aperture size below doesn't make sense!?
*/
shift = (u16) (temp>>16);
#ifdef ARTICIAS_DEBUG
printk(KERN_INFO PFX "[ARTICIAS] * temp = 0x%x, shift = 0x%x\n", temp, shift);
#endif
pci_write_config_word(agp_bridge->dev, ARTICIAS_TLB_BASE, shift);
/* Original code from MAI. */
/*
pci_write_config_word(agp_bridge->dev, ARTICIAS_APSIZE, (shift & current_size->size_value));
*/
/* Geri: I can't figure out how they want to configure the rest of the
* 20 bits TLB base address in the config register for the aperture
* size, so here is my code.
*/
/* Get the byte 1 from dword and mask it out with the aperture size. */
shift = (u16) (temp>>8);
shift &= ~(ARTICIAS_SIZE_MASK);
shift |= current_size->size_value;
pci_write_config_byte(agp_bridge->dev, ARTICIAS_APBASE, (u8) shift);
/* Original code from MAI. Get address to map too */
/*
pci_read_config_word(agp_bridge->dev, ARTICIAS_GATTBASE, (void *)&temp);
temp = temp & ARTICIAS_GATT_MASK;
*/
/* Get address to map too */
pci_read_config_dword(agp_bridge->dev, ARTICIAS_GATTBASE, (void *)&temp);
temp = temp & ARTICIAS_GATT_MASK;
agp_bridge->gart_bus_addr = temp;
/* GART control register */
/* Enable GART and bus concurrency */
pci_write_config_byte(agp_bridge->dev, ARTICIAS_GART_EN, 0x41);
/* Enable AGP operation */
pci_write_config_byte(agp_bridge->dev, ARTICIAS_AGP_EN, 0x01);
return 0;
}
static void articias_cleanup(void)
{
struct aper_size_info_8 *previous_size;
#ifdef ARTICIAS_DEBUG
printk(KERN_INFO PFX "[ARTICIAS] articias_cleanup()\n");
#endif
previous_size = A_SIZE_8(agp_bridge->previous_size);
pci_write_config_byte(agp_bridge->dev, ARTICIAS_APSIZE,
previous_size->size_value);
}
static void articias_tlbflush(struct agp_memory *mem)
{
/* pci_write_config_dword(agp_bridge->dev, ARTICIAS_GARTCTRL, 0x0000008f);
pci_write_config_dword(agp_bridge->dev, ARTICIAS_GARTCTRL, 0x0000000f);
*/
/* Geri: We need to do something here. There is a AGP TLB translation
* control bit (0x58:7) specified in the ArticiaP datasheet which may
* control TLB flushes. We have to check, if it exists also in the
* ArticiaS.
*/
#ifdef ARTICIAS_DEBUG
printk(KERN_INFO PFX "[ARTICIAS] agp_tlbflush()\n");
#endif
return;
}
static struct aper_size_info_8 articias_generic_sizes[7] =
{
/* size, num_entries, page_order, size_value */
/* Geri: added 256MB aperture size value. I think these are MB values,
* because the ArticiaP supports aperture sizes from 4kB to 256MB, but
* the default value is set to 4MB. Let's hope that the ArticiaS
* supports aperture sizes from 4MB to 256MB.
*/
{4, 1024, 1, 1},
{8, 2048, 1, 2},
{16, 4096, 2, 3},
{32, 8192, 3, 4},
{64, 16384, 4, 5},
{128, 32768, 5, 6},
{256, 65536, 6, 7},
/* Original code from MAI. */
/*
{4, 1024, 1, 1},
{8, 2048, 1, 2},
{16, 4096, 2, 3},
{32, 8192, 3, 4},
{64, 16384, 4, 5},
{128, 32768, 5, 6}
*/
};
static unsigned long articias_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
#ifdef ARTICIAS_DEBUG
printk(KERN_INFO PFX "[ARTICIAS] articias_mask_memory()\n");
#endif
return addr | agp_bridge->driver->masks[0].mask;
}
static struct gatt_mask articias_generic_masks[] =
{
/* Original code from MAI. */
{0x00000000, 0}
};
static struct agp_bridge_driver articias_driver = {
.owner = THIS_MODULE,
.aperture_sizes = articias_generic_sizes,
.size_type = U8_APER_SIZE,
/* Geri: Was 6 before. Added 256k entry for aperture size. */
.num_aperture_sizes = 7,
.configure = articias_configure,
.fetch_size = articias_fetch_size,
.cleanup = articias_cleanup,
.tlb_flush = articias_tlbflush,
.mask_memory = articias_mask_memory,
.masks = articias_generic_masks,
.agp_enable = agp_generic_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = agp_generic_create_gatt_table,
.free_gatt_table = agp_generic_free_gatt_table,
.insert_memory = agp_generic_insert_memory,
.remove_memory = agp_generic_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
};
static struct agp_device_ids articias_agp_device_ids[] __devinitdata =
{
{
.device_id = PCI_DEVICE_ID_MAI_ARTICIAS,
.chipset_name = "ArticiaS",
},
{ }, /* dummy final entry, always present */
};
static int __devinit agp_articias_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct agp_device_ids *devs = articias_agp_device_ids;
struct agp_bridge_data *bridge;
int j = 0;
u8 cap_ptr;
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
if (!cap_ptr)
return -ENODEV;
j = ent - agp_articias_pci_table;
printk (KERN_INFO PFX "Detected %s chipset\n", devs[j].chipset_name);
bridge = agp_alloc_bridge();
if (!bridge)
return -ENOMEM;
#ifdef ARTICIAS_DEBUG
/* Geri: Print all AGP relevant registers of the ArticiaS. */
printk(KERN_INFO PFX "[ARTICIAS] articias_print_agp_register()\n");
#endif
bridge->dev = pdev;
bridge->capndx = cap_ptr;
bridge->driver = &articias_driver;
return agp_add_bridge(bridge);
}
static void __devexit agp_articias_remove(struct pci_dev *pdev)
{
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
agp_remove_bridge(bridge);
agp_put_bridge(bridge);
}
#ifdef CONFIG_PM
static int agp_articias_suspend(struct pci_dev *pdev, pm_message_t state)
{
pci_save_state (pdev);
pci_set_power_state (pdev, PCI_D3hot);
return 0;
}
static int agp_articias_resume(struct pci_dev *pdev)
{
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
pci_set_power_state (pdev, PCI_D0);
pci_restore_state(pdev);
if (bridge->driver == &articias_driver)
return articias_configure();
return 0;
}
#endif /* CONFIG_PM */
/* must be the same order as name table above */
static struct pci_device_id agp_articias_pci_table[] = {
#define ID(x) \
{ \
.class = (PCI_CLASS_BRIDGE_HOST << 8), \
.class_mask = ~0, \
.vendor = PCI_VENDOR_ID_MAI, \
.device = x, \
.subvendor = PCI_ANY_ID, \
.subdevice = PCI_ANY_ID, \
}
ID(PCI_DEVICE_ID_MAI_ARTICIAS),
{ }
};
MODULE_DEVICE_TABLE(pci, agp_articias_pci_table);
static struct pci_driver agp_articias_pci_driver = {
.name = "agpgart-articias",
.id_table = agp_articias_pci_table,
.probe = agp_articias_probe,
.remove = agp_articias_remove,
#ifdef CONFIG_PM
.suspend = agp_articias_suspend,
.resume = agp_articias_resume,
#endif
};
static int __init agp_articias_init(void)
{
if (agp_off)
{
#ifdef ARTICIAS_DEBUG
printk(KERN_INFO PFX "[ARTICIAS] agp_articias_init return EINVAL.\n");
#endif
return -EINVAL;
}
#ifdef ARTICIAS_DEBUG
printk(KERN_INFO PFX "[ARTICIAS] agp_articias_init return pci driver struct.\n");
#endif
return pci_register_driver(&agp_articias_pci_driver);
}
static void __exit agp_articias_cleanup(void)
{
pci_unregister_driver(&agp_articias_pci_driver);
}
/* Debug function to check ArticiaS's AGP register configuration. Call before
* any AGP functionality is enabled! Otherwise it will destroy the previous
* configuration!
*/
static void articias_test_agp_register(struct pci_dev *pdev)
{
printk(KERN_INFO PFX "[ARTICIAS] articias_test_agp_register().\n");
printk(KERN_INFO PFX "[ARTICIAS] RW Addr Register Value\n");
printk(KERN_INFO PFX "[ARTICIAS] -----------------------------------------\n);
/* R = Read
* W = Write
* RO = Read only - no write test
* RT = Read test value
*/
/* Test register address space 0x10..0x13. */
u32 agp_gart_base_dword_init = 0;
u32 agp_gart_base_dword_test = 0;
/* Read out initial AGP GART base register configuration. */
pci_read_config_dword(pdev, 0x10, (void *)&agp_gart_base_dword_init);
printk(KERN_INFO PFX "[ARTICIAS] R 0x10 agp_gart_base 0x%x\n", (u32)agp_gart_base_dword_init);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 GART memory space\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2:1 GART addess type\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 3 Memory prefetch\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 11:4 Reserved\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 31:12 GART base address\n");
/* Write register to find out bit assignments in the register. */
/* Mask register init value with new settings. */
agp_gart_base_dword_test = agp_gart_base_dword_init | 0xFFFFF000;
printk(KERN_INFO PFX "[ARTICIAS] W 0x10 agp_gart_base 0x%x\n", (u32)agp_gart_base_dword_test);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 GART memory space def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2:1 GART addess type def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 3 Memory prefetch def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 11:4 Reserved def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 31:12 GART base address 0xFFFFF\n");
pci_write_config_dword(pdev, 0x10, agp_gart_base_dword_test);
agp_gart_base_dword_test = 0;
/* Read back the register test configuration. */
pci_read_config_dword(pdev, 0x10, (void *)&agp_gart_base_dword_test);
printk(KERN_INFO PFX "[ARTICIAS] RT 0x10 agp_gart_base 0x%x\n", (u32)agp_gart_base_dword_test);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 GART memory space def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2:1 GART addess type def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 3 Memory prefetch def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 11:4 Reserved def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 31:12 GART base address 0xFFFFF\n");
agp_gart_base_dword_test = 0;
/* Restore initial register content. */
pci_write_config_dword(pdev, 0x10, agp_gart_base_dword_init);
pci_read_config_dword(pdev, 0x10, (void *)&agp_gart_base_dword_test);
if(agp_gart_base_dword_test != agp_gart_dword_init)
{
printk(KERN_INFO PFX "[ARTICIAS] ERROR: Could not restore initial register setting!\n");
}
/* Output capability pointer register. */
u8 byte_registers = 0;
pci_read_config_byte(pdev, 0x34, (void *)&byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x34 cap_pointer 0x%x\n", (u8)byte_registers);
/* Output capability identifier register. */
byte_registers = 0;
pci_read_config_byte(pdev, 0x40, (void *)&byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x40 cap_identifier 0x%x\n", (u8)byte_registers);
/* Output AGP interface specification revision number. */
byte_registers = 0;
pci_read_config_byte(pdev, 0x42, (void *)&byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x42 agp_int_rev 0x%x\n", (u8)byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 3:0 AGP interface spec minor rev\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7:4 AGP interface spec major rev\n");
/* Output AGP operation status 0/1 register. */
u16 word_registers = 0;
pci_read_config_word(pdev, 0x44, (void *)&word_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x44 agp_op_stat01 0x%x\n", (u16)word_registers);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 AGP 1X transfer rate support\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 1 AGP 2X transfer rate support\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2 AGP 4X transfer rate support\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 8:3 Reserved\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 9 AGP Sideband Addressing support\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 15:10 Reserved\n");
/* Output AGP operation status 2 register. */
byte_registers = 0;
pci_read_config_byte(pdev, 0x47, (void *)&byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x47 agp_op_stat2 0x%x\n", (u8)byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7:0 AGP maximum number of commands\n");
/* Test AGP command register. */
u16 agp_cmd_word_init = 0;
u16 agp_cmd_word_test = 0;
/* Read out initial AGP command register configuration. */
pci_read_config_word(pdev, 0x48, (void *)&agp_cmd_word_init);
printk(KERN_INFO PFX "[ARTICIAS] R 0x48 agp_cmd 0x%x\n", (u16)agp_cmd_word_init);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2:0 AGP 1x/2x/4x\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7:3 Reserved\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 8 AGP operation\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 9 SBAddressing\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 15:10 Reserved\n");
/* Write register to find out bit assignments in the register. */
/* Mask register init value with new settings. We leave the AGP
* transfer rate as it is, because we know that the ArticiaS only
* supports 1x and 2x transfer rates. Also we don't set the AGP
* operation enable bit, because AGP mode is not setup yet!
*/
agp_cmd_word_test = agp_cmd_word_init | 0xFEF8;
printk(KERN_INFO PFX "[ARTICIAS] W 0x48 agp_cmd 0x%x\n", (u16)agp_cmd_word_test);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2:0 AGP 1x/2x/4x def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7:3 Reserved 0xFF\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 8 AGP operation def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 9 SBAddressing 0x1\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 15:10 Reserved 0xFF\n");
pci_write_config_word(pdev, 0x48, agp_cmd_word_test);
agp_cmd_word_test = 0;
/* Read back the register test configuration. */
pci_read_config_word(pdev, 0x48, (void *)&agp_cmd_word_test);
printk(KERN_INFO PFX "[ARTICIAS] RT 0x48 agp_cmd 0x%x\n", (u16)agp_cmd_word_test);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2:0 AGP 1x/2x/4x 0x2\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7:3 Reserved 0x00\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 8 AGP operation 0x0\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 9 SBAddressing 0x1\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 15:10 Reserved 0x00\n");
agp_cmd_word_test = 0;
/* Restore initial register content. */
pci_write_config_word(pdev, 0x48, agp_cmd_word_init);
pci_read_config_word(pdev, 0x48, (void *)&agp_cmd_word_test);
if(agp_cmd_word_test != agp_cmd_word_init)
{
printk(KERN_INFO PFX "[ARTICIAS] ERROR: Could not restore initial register setting!\n");
}
/* Test bus 1 access control register (0x58-0x5B). */
u32 agp_bus1_dword_init = 0;
u32 agp_bus1_dword_test = 0;
/* Read out initial bus 1 access control register configuration. */
pci_read_config_dword(pdev, 0x58, (void *)&agp_bus1_dword_init);
printk(KERN_INFO PFX "[ARTICIAS] R 0x58 agp_bus1 0x%x\n", (u32)agp_bus1_dword_init);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 Byte enable check\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 1 AGP extension mode\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2 Graphic device AGP/PCI\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 5:3 Reserved\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 6 GART transfer control\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7 AGP TLB translation control\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 11:8 GART size selection (\n");
printk(KERN_INFO PFX "[ARTICIAS] * >>> 10:8 for ArticiaS(\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 31:12 AGP TLB base address\n");
printk(KERN_INFO PFX "[ARTICIAS] * >>> 31:16 for ArticiaS?\n");
/* Write register to find out bit assignments in the register. */
/* Mask register init value with new settings. We set the AGP TLB base
* address (to check the size of the field), the AGP TLB translation
* control bit (because its not clear if the ArticiaS supports it) and
* the GART size selection bits.
*/
agp_bus1_dword_test = agp_bus1_dword_init | 0xFFFFFFB8;
printk(KERN_INFO PFX "[ARTICIAS] W 0x58 agp_bus1 0x%x\n", (u32)agp_bus1_dword_test);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 Byte enable check def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 1 AGP extension mode def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2 Graphic device def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 5:3 Reserved 0x3\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 6 GART transfer def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7 AGP TLB transl. 0x1\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 11:8 GART size 0xF\n");
printk(KERN_INFO PFX "[ARTICIAS] * >>> 10:8 for ArticiaS(\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 31:12 AGP TLB base 0FFFFF\n");
printk(KERN_INFO PFX "[ARTICIAS] * >>> 31:16 for ArticiaS?\n");
pci_write_config_dword(pdev, 0x58, agp_bus1_dword_test);
agp_bus1_dword_test = 0;
/* Read back the register test configuration. */
pci_read_config_dword(pdev, 0x58, (void *)&agp_bus1_dword_test);
printk(KERN_INFO PFX "[ARTICIAS] RT 0x58 agp_bus1 0x%x\n", (u32)agp_bus1_dword_test);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 Byte enable check def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 1 AGP extension mode def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2 Graphic device def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 5:3 Reserved 0x0\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 6 GART transfer def\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7 AGP TLB transl. 0x1\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 11:8 GART size 0x7\n");
printk(KERN_INFO PFX "[ARTICIAS] * >>> 10:8 for ArticiaS(\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 31:12 AGP TLB base 0FFFF0\n");
printk(KERN_INFO PFX "[ARTICIAS] * >>> 31:16 for ArticiaS?\n");;
agp_bus1_dword_test = 0;
/* Restore initial register content. */
pci_write_config_dword(pdev, 0x58, agp_bus1_dword_init);
pci_read_config_dword(pdev, 0x58, (void *)&agp_bus1_dword_test);
if(agp_bus1_dword_test != agp_bus1_dword_init)
{
printk(KERN_INFO PFX "[ARTICIAS] ERROR: Could not restore initial register setting!\n");
}
printk(KERN_INFO PFX "[ARTICIAS] End of articias_test_agp_register().\n");
}
static void articias_print_agp_register(struct pci_dev *pdev)
{
printk(KERN_INFO PFX "[ARTICIAS] articias_print_agp_register().\n");
printk(KERN_INFO PFX "[ARTICIAS] RW Addr Register Value\n");
printk(KERN_INFO PFX "[ARTICIAS] -----------------------------------------\n);
/* R = Read */
/* Output GART base address register (0x10..0x13). */
u32 dword_register = 0;
pci_read_config_dword(pdev, 0x10, (void *)&dword_register);
printk(KERN_INFO PFX "[ARTICIAS] R 0x10 agp_gart_base 0x%x\n", (u32)dword_register);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 GART memory space\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2:1 GART addess type\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 3 Memory prefetch\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 11:4 Reserved\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 31:12 GART base address\n");
/* Output capability pointer register. */
u8 byte_registers = 0;
pci_read_config_byte(pdev, 0x34, (void *)&byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x34 cap_pointer 0x%x\n", (u8)byte_registers);
/* Output capability identifier register. */
byte_registers = 0;
pci_read_config_byte(pdev, 0x40, (void *)&byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x40 cap_identifier 0x%x\n", (u8)byte_registers);
/* Output AGP interface specification revision number. */
byte_registers = 0;
pci_read_config_byte(pdev, 0x42, (void *)&byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x42 agp_int_rev 0x%x\n", (u8)byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 3:0 AGP interface spec minor rev\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7:4 AGP interface spec major rev\n");
/* Output AGP operation status 0/1 register. */
u16 word_registers = 0;
pci_read_config_word(pdev, 0x44, (void *)&word_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x44 agp_op_stat01 0x%x\n", (u16)word_registers);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 AGP 1X transfer rate support\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 1 AGP 2X transfer rate support\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2 AGP 4X transfer rate support\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 8:3 Reserved\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 9 AGP Sideband Addressing support\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 15:10 Reserved\n");
/* Output AGP operation status 2 register. */
byte_registers = 0;
pci_read_config_byte(pdev, 0x47, (void *)&byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] RO 0x47 agp_op_stat2 0x%x\n", (u8)byte_registers);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7:0 AGP maximum number of commands\n");
/* Output AGP command register. */
word_registers = 0;
pci_read_config_word(pdev, 0x48, (void *)&word_registers);
printk(KERN_INFO PFX "[ARTICIAS] R 0x48 agp_cmd 0x%x\n", (u16)word_registers);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2:0 AGP 1x/2x/4x\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7:3 Reserved\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 8 AGP operation\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 9 SBAddressing\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 15:10 Reserved\n");
/* Output bus 1 access control register (0x58-0x5B). */
dword_registers = 0;
pci_read_config_dword(pdev, 0x58, (void *)&dword_registers);
printk(KERN_INFO PFX "[ARTICIAS] R 0x58 agp_bus1 0x%x\n", (u32)dword_registers);
printk(KERN_INFO PFX "[ARTICIAS] * Decoding:\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 0 Byte enable check\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 1 AGP extension mode\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 2 Graphic device AGP/PCI\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 5:3 Reserved\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 6 GART transfer control\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 7 AGP TLB translation control\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 11:8 GART size selection (\n");
printk(KERN_INFO PFX "[ARTICIAS] * >>> 10:8 for ArticiaS(\n");
printk(KERN_INFO PFX "[ARTICIAS] * Bit 31:12 AGP TLB base address\n");
printk(KERN_INFO PFX "[ARTICIAS] * >>> 31:16 for ArticiaS?\n");
}
module_init(agp_articias_init);
module_exit(agp_articias_cleanup);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
reply other threads:[~2006-01-04 11:09 UTC|newest]
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