From: Kumar Gala <galak@kernel.crashing.org>
To: Paul Mackerras <paulus@samba.org>
Cc: linuxppc-dev list <linuxppc-dev@ozlabs.org>,
linuxppc64-dev <linuxppc64-dev@ozlabs.org>,
Steve Munroe <sjmunroe@us.ibm.com>
Subject: Re: [PATCH] implement AT_PLATFORM for powerpc
Date: Wed, 11 Jan 2006 08:43:04 -0600 [thread overview]
Message-ID: <C056E42C-4362-4020-8097-E8662017A27A@kernel.crashing.org> (raw)
In-Reply-To: <17348.50913.414568.263736@cargo.ozlabs.ibm.com>
Paul,
This reminds me do we have a bit for having/not having the load/store
string instructions. If memory serves me there were some discussions
of looking at "depreciating" the instructions from the architecture.
Freescale Book-E implementations already do NOT implement them. I
doubt that Freescale will over implement these instructions ever again.
-k
On Jan 11, 2006, at 2:50 AM, Paul Mackerras wrote:
> Eugene Surovegin writes:
>
>> I checked 44x user manuals I have:
>>
>> 440GP doesn't have isel
>> 440GX, 440EP, 440SP, 440SPe, 440GR have it.
>
> Thanks, that's helpful. Do you know if 440{GX,EP,SP,SPe,GR} implement
> all of the 32-bit user-mode instructions in Book E?
>
> How do mbar and msync work on those processors? As mbar and msync (as
> defined in Book E) or as eieio and sync?
>
> Do the 440* processors in fact claim Book E compliance?
>
> Thanks,
> Paul.
> _______________________________________________
> Linuxppc64-dev mailing list
> Linuxppc64-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc64-dev
prev parent reply other threads:[~2006-01-11 14:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-01-11 4:27 [PATCH] implement AT_PLATFORM for powerpc Paul Mackerras
2006-01-11 4:48 ` Kumar Gala
2006-01-11 5:08 ` Paul Mackerras
2006-01-11 6:10 ` Kumar Gala
2006-01-11 7:10 ` Eugene Surovegin
2006-01-11 8:50 ` Paul Mackerras
2006-01-11 9:19 ` Eugene Surovegin
2006-01-11 14:43 ` Kumar Gala [this message]
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