From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-Id: From: Kumar Gala To: linuxppcdev@lists.qbjnet.com In-Reply-To: <20080117222624.19372.qmail@kunk.qbjnet.com> Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes Mime-Version: 1.0 (Apple Message framework v915) Subject: Re: L3CR Date: Thu, 17 Jan 2008 21:41:34 -0600 References: <20080117222624.19372.qmail@kunk.qbjnet.com> Cc: Linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Jan 17, 2008, at 4:26 PM, linuxppcdev@lists.qbjnet.com wrote: > It there a l3cr parameter? It's not in the kernel documentation. I'm > trying to enable L2 and L3 cache on a G4 cpu upgrade board in a > powermac. > >> From OSX I was able to get the values of: > l2cr = 0x80000000 > and > l3cr = 0x9F020300 > > from a cache config utility. I've seen references to l3cr setting on > bsd lists but not for linux. > > Thanks... have you looked in /proc/sys/kernel/l[2,3]cr? (can't remember if we had a l3cr as well) - k