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Sat, 10 Jul 2021 02:50:58 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 18883AE051; Sat, 10 Jul 2021 02:50:58 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0AED2AE04D; Sat, 10 Jul 2021 02:50:57 +0000 (GMT) Received: from [9.79.176.228] (unknown [9.79.176.228]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Sat, 10 Jul 2021 02:50:56 +0000 (GMT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.120.23.2.6\)) Subject: Re: [RFC PATCH 10/43] powerpc/64s: Always set PMU control registers to frozen/disabled when not in use From: Athira Rajeev In-Reply-To: <20210622105736.633352-11-npiggin@gmail.com> Date: Sat, 10 Jul 2021 08:20:54 +0530 Content-Transfer-Encoding: quoted-printable Message-Id: References: <20210622105736.633352-1-npiggin@gmail.com> <20210622105736.633352-11-npiggin@gmail.com> To: Nicholas Piggin X-Mailer: Apple Mail (2.3608.120.23.2.6) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: o6RgV5VuVuOgehlUJdVPrBdu-XXRmFFs X-Proofpoint-GUID: FK4G-T8U__xOyiHE9quDJutl50Fu6q4K X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-10_02:2021-07-09, 2021-07-10 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 mlxscore=0 spamscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107100013 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" > On 22-Jun-2021, at 4:27 PM, Nicholas Piggin wrote: >=20 > KVM PMU management code looks for particular frozen/disabled bits in > the PMU registers so it knows whether it must clear them when coming > out of a guest or not. Setting this up helps KVM make these = optimisations > without getting confused. Longer term the better approach might be to > move guest/host PMU switching to the perf subsystem. >=20 > Signed-off-by: Nicholas Piggin > --- > arch/powerpc/kernel/cpu_setup_power.c | 4 ++-- > arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++--- > arch/powerpc/kvm/book3s_hv.c | 5 +++++ > arch/powerpc/perf/core-book3s.c | 7 +++++++ > 4 files changed, 17 insertions(+), 5 deletions(-) >=20 > diff --git a/arch/powerpc/kernel/cpu_setup_power.c = b/arch/powerpc/kernel/cpu_setup_power.c > index a29dc8326622..3dc61e203f37 100644 > --- a/arch/powerpc/kernel/cpu_setup_power.c > +++ b/arch/powerpc/kernel/cpu_setup_power.c > @@ -109,7 +109,7 @@ static void init_PMU_HV_ISA207(void) > static void init_PMU(void) > { > mtspr(SPRN_MMCRA, 0); > - mtspr(SPRN_MMCR0, 0); > + mtspr(SPRN_MMCR0, MMCR0_FC); > mtspr(SPRN_MMCR1, 0); > mtspr(SPRN_MMCR2, 0); > } > @@ -123,7 +123,7 @@ static void init_PMU_ISA31(void) > { > mtspr(SPRN_MMCR3, 0); > mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE); > - mtspr(SPRN_MMCR0, MMCR0_PMCCEXT); > + mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMCCEXT); > } >=20 > /* > diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c = b/arch/powerpc/kernel/dt_cpu_ftrs.c > index 0a6b36b4bda8..06a089fbeaa7 100644 > --- a/arch/powerpc/kernel/dt_cpu_ftrs.c > +++ b/arch/powerpc/kernel/dt_cpu_ftrs.c > @@ -353,7 +353,7 @@ static void init_pmu_power8(void) > } >=20 > mtspr(SPRN_MMCRA, 0); > - mtspr(SPRN_MMCR0, 0); > + mtspr(SPRN_MMCR0, MMCR0_FC); > mtspr(SPRN_MMCR1, 0); > mtspr(SPRN_MMCR2, 0); > mtspr(SPRN_MMCRS, 0); > @@ -392,7 +392,7 @@ static void init_pmu_power9(void) > mtspr(SPRN_MMCRC, 0); >=20 > mtspr(SPRN_MMCRA, 0); > - mtspr(SPRN_MMCR0, 0); > + mtspr(SPRN_MMCR0, MMCR0_FC); > mtspr(SPRN_MMCR1, 0); > mtspr(SPRN_MMCR2, 0); > } > @@ -428,7 +428,7 @@ static void init_pmu_power10(void) >=20 > mtspr(SPRN_MMCR3, 0); > mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE); > - mtspr(SPRN_MMCR0, MMCR0_PMCCEXT); > + mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMCCEXT); > } >=20 > static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f) > diff --git a/arch/powerpc/kvm/book3s_hv.c = b/arch/powerpc/kvm/book3s_hv.c > index 1f30f98b09d1..f7349d150828 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -2593,6 +2593,11 @@ static int kvmppc_core_vcpu_create_hv(struct = kvm_vcpu *vcpu) > #endif > #endif > vcpu->arch.mmcr[0] =3D MMCR0_FC; > + if (cpu_has_feature(CPU_FTR_ARCH_31)) { > + vcpu->arch.mmcr[0] |=3D MMCR0_PMCCEXT; > + vcpu->arch.mmcra =3D MMCRA_BHRB_DISABLE; > + } > + > vcpu->arch.ctrl =3D CTRL_RUNLATCH; > /* default to host PVR, since we can't spoof it */ > kvmppc_set_pvr_hv(vcpu, mfspr(SPRN_PVR)); > diff --git a/arch/powerpc/perf/core-book3s.c = b/arch/powerpc/perf/core-book3s.c > index 51622411a7cc..e33b29ec1a65 100644 > --- a/arch/powerpc/perf/core-book3s.c > +++ b/arch/powerpc/perf/core-book3s.c > @@ -1361,6 +1361,13 @@ static void power_pmu_enable(struct pmu *pmu) > goto out; >=20 > if (cpuhw->n_events =3D=3D 0) { > + if (cpu_has_feature(CPU_FTR_ARCH_31)) { > + mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE); > + mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMCCEXT); > + } else { > + mtspr(SPRN_MMCRA, 0); > + mtspr(SPRN_MMCR0, MMCR0_FC); > + } Hi Nick, We are setting these bits in =E2=80=9Cpower_pmu_disable=E2=80=9D = function. And disable will be called before any event gets = deleted/stopped. Can you please help to understand why this is needed in = power_pmu_enable path also ? Thanks Athira > ppc_set_pmu_inuse(0); > goto out; > } > --=20 > 2.23.0 >=20