* [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition
2020-09-16 10:16 [PATCH 0/3] ASoC: fsl_sai: update the register list Shengjiu Wang
@ 2020-09-16 10:16 ` Shengjiu Wang
2020-09-16 17:03 ` Fabio Estevam
2020-09-17 1:44 ` Nicolin Chen
2020-09-16 10:16 ` [PATCH 2/3] ASoC: fsl_sai: Add fsl_sai_check_version function Shengjiu Wang
` (2 subsequent siblings)
3 siblings, 2 replies; 10+ messages in thread
From: Shengjiu Wang @ 2020-09-16 10:16 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, festevam, broonie, perex, tiwai,
alsa-devel, lgirdwood
Cc: linuxppc-dev, linux-kernel
On i.MX850/i.MX815/i.MX845 platform, the sai IP is upgraded.
There are some new registers and new bit definition. This
patch is to complete the register list.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 23 ++++++++++++++++
sound/soc/fsl/fsl_sai.h | 59 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 82 insertions(+)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index b2d65e53dbc4..24ca528ca2be 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -796,6 +796,8 @@ static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
{FSL_SAI_RCR4(8), 0},
{FSL_SAI_RCR5(8), 0},
{FSL_SAI_RMR, 0},
+ {FSL_SAI_MCTL, 0},
+ {FSL_SAI_MDIV, 0},
};
static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
@@ -836,6 +838,18 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_RFR6:
case FSL_SAI_RFR7:
case FSL_SAI_RMR:
+ case FSL_SAI_MCTL:
+ case FSL_SAI_MDIV:
+ case FSL_SAI_VERID:
+ case FSL_SAI_PARAM:
+ case FSL_SAI_TTCTN:
+ case FSL_SAI_RTCTN:
+ case FSL_SAI_TTCTL:
+ case FSL_SAI_TBCTN:
+ case FSL_SAI_TTCAP:
+ case FSL_SAI_RTCTL:
+ case FSL_SAI_RBCTN:
+ case FSL_SAI_RTCAP:
return true;
default:
return false;
@@ -850,6 +864,10 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
return true;
+ /* Set VERID and PARAM be volatile for reading value in probe */
+ if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
+ return true;
+
switch (reg) {
case FSL_SAI_TFR0:
case FSL_SAI_TFR1:
@@ -903,6 +921,10 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_TDR7:
case FSL_SAI_TMR:
case FSL_SAI_RMR:
+ case FSL_SAI_MCTL:
+ case FSL_SAI_MDIV:
+ case FSL_SAI_TTCTL:
+ case FSL_SAI_RTCTL:
return true;
default:
return false;
@@ -951,6 +973,7 @@ static int fsl_sai_probe(struct platform_device *pdev)
if (sai->soc_data->reg_offset == 8) {
fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
+ fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
fsl_sai_regmap_config.num_reg_defaults =
ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
}
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 736a437450c8..d16fc4241f41 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -14,6 +14,8 @@
SNDRV_PCM_FMTBIT_S32_LE)
/* SAI Register Map Register */
+#define FSL_SAI_VERID 0x00 /* SAI Version ID Register */
+#define FSL_SAI_PARAM 0x04 /* SAI Parameter Register */
#define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
#define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
#define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
@@ -37,6 +39,10 @@
#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
+#define FSL_SAI_TTCTL 0x70 /* SAI Transmit Timestamp Control Register */
+#define FSL_SAI_TTCTN 0x74 /* SAI Transmit Timestamp Counter Register */
+#define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */
+#define FSL_SAI_TTCAP 0x7C /* SAI Transmit Timestamp Capture */
#define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
#define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
#define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
@@ -60,6 +66,13 @@
#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
+#define FSL_SAI_RTCTL 0xf0 /* SAI Receive Timestamp Control Register */
+#define FSL_SAI_RTCTN 0xf4 /* SAI Receive Timestamp Counter Register */
+#define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
+#define FSL_SAI_RTCAP 0xfc /* SAI Receive Timestamp Capture */
+
+#define FSL_SAI_MCTL 0x100 /* SAI MCLK Control Register */
+#define FSL_SAI_MDIV 0x104 /* SAI MCLK Divide Register */
#define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
#define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
@@ -73,6 +86,7 @@
/* SAI Transmit/Receive Control Register */
#define FSL_SAI_CSR_TERE BIT(31)
+#define FSL_SAI_CSR_SE BIT(30)
#define FSL_SAI_CSR_FR BIT(25)
#define FSL_SAI_CSR_SR BIT(24)
#define FSL_SAI_CSR_xF_SHIFT 16
@@ -106,6 +120,7 @@
#define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
#define FSL_SAI_CR2_BCP BIT(25)
#define FSL_SAI_CR2_BCD_MSTR BIT(24)
+#define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */
#define FSL_SAI_CR2_DIV_MASK 0xff
/* SAI Transmit and Receive Configuration 3 Register */
@@ -115,6 +130,13 @@
#define FSL_SAI_CR3_WDFL_MASK 0x1f
/* SAI Transmit and Receive Configuration 4 Register */
+
+#define FSL_SAI_CR4_FCONT BIT(28)
+#define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
+#define FSL_SAI_CR4_FCOMB_SOFT BIT(27)
+#define FSL_SAI_CR4_FCOMB_MASK (0x3 << 26)
+#define FSL_SAI_CR4_FPACK_8 (0x2 << 24)
+#define FSL_SAI_CR4_FPACK_16 (0x3 << 24)
#define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
@@ -134,6 +156,43 @@
#define FSL_SAI_CR5_FBT(x) ((x) << 8)
#define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
+/* SAI MCLK Control Register */
+#define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */
+#define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24)
+#define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24)
+#define FSL_SAI_MCTL_MSEL_BUS 0
+#define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24)
+#define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25)
+#define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25))
+#define FSL_SAI_MCTL_DIV_EN BIT(23)
+#define FSL_SAI_MCTL_DIV_MASK 0xFF
+
+/* SAI VERID Register */
+#define FSL_SAI_VERID_MAJOR_SHIFT 24
+#define FSL_SAI_VERID_MAJOR_MASK GENMASK(31, 24)
+#define FSL_SAI_VERID_MINOR_SHIFT 16
+#define FSL_SAI_VERID_MINOR_MASK GENMASK(23, 16)
+#define FSL_SAI_VERID_FEATURE_SHIFT 0
+#define FSL_SAI_VERID_FEATURE_MASK GENMASK(15, 0)
+#define FSL_SAI_VERID_EFIFO_EN BIT(0)
+#define FSL_SAI_VERID_TSTMP_EN BIT(1)
+
+/* SAI PARAM Register */
+#define FSL_SAI_PARAM_SPF_SHIFT 16
+#define FSL_SAI_PARAM_SPF_MASK GENMASK(19, 16)
+#define FSL_SAI_PARAM_WPF_SHIFT 8
+#define FSL_SAI_PARAM_WPF_MASK GENMASK(11, 8)
+#define FSL_SAI_PARAM_DLN_MASK GENMASK(3, 0)
+
+/* SAI MCLK Divide Register */
+#define FSL_SAI_MDIV_MASK 0xFFFFF
+
+/* SAI timestamp and bitcounter */
+#define FSL_SAI_xTCTL_TSEN BIT(0)
+#define FSL_SAI_xTCTL_TSINC BIT(1)
+#define FSL_SAI_xTCTL_RTSC BIT(8)
+#define FSL_SAI_xTCTL_RBC BIT(9)
+
/* SAI type */
#define FSL_SAI_DMA BIT(0)
#define FSL_SAI_USE_AC97 BIT(1)
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition
2020-09-16 10:16 ` [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition Shengjiu Wang
@ 2020-09-16 17:03 ` Fabio Estevam
2020-09-17 1:44 ` Nicolin Chen
1 sibling, 0 replies; 10+ messages in thread
From: Fabio Estevam @ 2020-09-16 17:03 UTC (permalink / raw)
To: Shengjiu Wang
Cc: Linux-ALSA, Timur Tabi, Xiubo Li, Liam Girdwood, Takashi Iwai,
Jaroslav Kysela, Nicolin Chen, Mark Brown, linuxppc-dev,
linux-kernel
Hi Shengjiu,
On Wed, Sep 16, 2020 at 7:23 AM Shengjiu Wang <shengjiu.wang@nxp.com> wrote:
>
> On i.MX850/i.MX815/i.MX845 platform, the sai IP is upgraded.
Please avoid such internal SoC namings and use i.MX8MQ/i.MX8MN/iMX8MM instead.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition
2020-09-16 10:16 ` [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition Shengjiu Wang
2020-09-16 17:03 ` Fabio Estevam
@ 2020-09-17 1:44 ` Nicolin Chen
1 sibling, 0 replies; 10+ messages in thread
From: Nicolin Chen @ 2020-09-17 1:44 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, timur, Xiubo.Lee, lgirdwood, linuxppc-dev, tiwai,
perex, broonie, festevam, linux-kernel
On Wed, Sep 16, 2020 at 06:16:25PM +0800, Shengjiu Wang wrote:
> On i.MX850/i.MX815/i.MX845 platform, the sai IP is upgraded.
> There are some new registers and new bit definition. This
> patch is to complete the register list.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Change itself looks good.
Can add once fixing the commit message:
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] ASoC: fsl_sai: Add fsl_sai_check_version function
2020-09-16 10:16 [PATCH 0/3] ASoC: fsl_sai: update the register list Shengjiu Wang
2020-09-16 10:16 ` [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition Shengjiu Wang
@ 2020-09-16 10:16 ` Shengjiu Wang
2020-09-17 1:49 ` Nicolin Chen
2020-09-16 10:16 ` [PATCH 3/3] ASoC: fsl_sai: Set MCLK input or output direction Shengjiu Wang
2020-09-16 11:47 ` [PATCH 0/3] ASoC: fsl_sai: update the register list Fabio Estevam
3 siblings, 1 reply; 10+ messages in thread
From: Shengjiu Wang @ 2020-09-16 10:16 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, festevam, broonie, perex, tiwai,
alsa-devel, lgirdwood
Cc: linuxppc-dev, linux-kernel
fsl_sai_check_version can help to parse the version info
in VERID and PARAM registers.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 47 +++++++++++++++++++++++++++++++++++++++++
sound/soc/fsl/fsl_sai.h | 28 ++++++++++++++++++++++++
2 files changed, 75 insertions(+)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 24ca528ca2be..738b4dda7847 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -946,6 +946,48 @@ static struct regmap_config fsl_sai_regmap_config = {
.cache_type = REGCACHE_FLAT,
};
+static int fsl_sai_check_version(struct device *dev)
+{
+ struct fsl_sai *sai = dev_get_drvdata(dev);
+ unsigned char ofs = sai->soc_data->reg_offset;
+ unsigned int val;
+ int ret;
+
+ if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
+ return 0;
+
+ ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
+ if (ret < 0)
+ return ret;
+
+ dev_dbg(dev, "VERID: 0x%016X\n", val);
+
+ sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >>
+ FSL_SAI_VERID_MAJOR_SHIFT;
+ sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >>
+ FSL_SAI_VERID_MINOR_SHIFT;
+ sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
+
+ ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
+ if (ret < 0)
+ return ret;
+
+ dev_dbg(dev, "PARAM: 0x%016X\n", val);
+
+ /* Max slots per frame, power of 2 */
+ sai->param.slot_num = 1 <<
+ ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
+
+ /* Words per fifo, power of 2 */
+ sai->param.fifo_depth = 1 <<
+ ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
+
+ /* Number of datalines implemented */
+ sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
+
+ return 0;
+}
+
static int fsl_sai_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -1070,6 +1112,11 @@ static int fsl_sai_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, sai);
+ /* Get sai version */
+ ret = fsl_sai_check_version(&pdev->dev);
+ if (ret < 0)
+ dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret);
+
pm_runtime_enable(&pdev->dev);
regcache_cache_only(sai->regmap, true);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index d16fc4241f41..ba7425a9e217 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -223,6 +223,32 @@ struct fsl_sai_soc_data {
unsigned int reg_offset;
};
+/**
+ * struct fsl_sai_verid - version id data
+ * @major: major version number
+ * @minor: minor version number
+ * @feature: feature specification number
+ * 0000000000000000b - Standard feature set
+ * 0000000000000000b - Standard feature set
+ */
+struct fsl_sai_verid {
+ u32 major;
+ u32 minor;
+ u32 feature;
+};
+
+/**
+ * struct fsl_sai_param - parameter data
+ * @slot_num: The maximum number of slots per frame
+ * @fifo_depth: The number of words in each FIFO (depth)
+ * @dataline: The number of datalines implemented
+ */
+struct fsl_sai_param {
+ u32 slot_num;
+ u32 fifo_depth;
+ u32 dataline;
+};
+
struct fsl_sai {
struct platform_device *pdev;
struct regmap *regmap;
@@ -243,6 +269,8 @@ struct fsl_sai {
const struct fsl_sai_soc_data *soc_data;
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct fsl_sai_verid verid;
+ struct fsl_sai_param param;
};
#define TX 1
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/3] ASoC: fsl_sai: Add fsl_sai_check_version function
2020-09-16 10:16 ` [PATCH 2/3] ASoC: fsl_sai: Add fsl_sai_check_version function Shengjiu Wang
@ 2020-09-17 1:49 ` Nicolin Chen
0 siblings, 0 replies; 10+ messages in thread
From: Nicolin Chen @ 2020-09-17 1:49 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, timur, Xiubo.Lee, lgirdwood, linuxppc-dev, tiwai,
perex, broonie, festevam, linux-kernel
On Wed, Sep 16, 2020 at 06:16:26PM +0800, Shengjiu Wang wrote:
> fsl_sai_check_version can help to parse the version info
> in VERID and PARAM registers.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> sound/soc/fsl/fsl_sai.c | 47 +++++++++++++++++++++++++++++++++++++++++
> sound/soc/fsl/fsl_sai.h | 28 ++++++++++++++++++++++++
> 2 files changed, 75 insertions(+)
>
> diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> index 24ca528ca2be..738b4dda7847 100644
> --- a/sound/soc/fsl/fsl_sai.c
> +++ b/sound/soc/fsl/fsl_sai.c
> @@ -946,6 +946,48 @@ static struct regmap_config fsl_sai_regmap_config = {
> .cache_type = REGCACHE_FLAT,
> };
>
> +static int fsl_sai_check_version(struct device *dev)
> +{
> + struct fsl_sai *sai = dev_get_drvdata(dev);
> + unsigned char ofs = sai->soc_data->reg_offset;
> + unsigned int val;
> + int ret;
> +
> + if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
> + return 0;
> +
> + ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
> + if (ret < 0)
> + return ret;
> +
> + dev_dbg(dev, "VERID: 0x%016X\n", val);
> +
> + sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >>
> + FSL_SAI_VERID_MAJOR_SHIFT;
> + sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >>
> + FSL_SAI_VERID_MINOR_SHIFT;
> + sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
> +
> + ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
> + if (ret < 0)
> + return ret;
> +
> + dev_dbg(dev, "PARAM: 0x%016X\n", val);
> +
> + /* Max slots per frame, power of 2 */
> + sai->param.slot_num = 1 <<
> + ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
> +
> + /* Words per fifo, power of 2 */
> + sai->param.fifo_depth = 1 <<
> + ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
> +
> + /* Number of datalines implemented */
> + sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
> +
> + return 0;
> +}
> +
> static int fsl_sai_probe(struct platform_device *pdev)
> {
> struct device_node *np = pdev->dev.of_node;
> @@ -1070,6 +1112,11 @@ static int fsl_sai_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, sai);
>
> + /* Get sai version */
> + ret = fsl_sai_check_version(&pdev->dev);
> + if (ret < 0)
> + dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret);
> +
> pm_runtime_enable(&pdev->dev);
> regcache_cache_only(sai->regmap, true);
>
> diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
> index d16fc4241f41..ba7425a9e217 100644
> --- a/sound/soc/fsl/fsl_sai.h
> +++ b/sound/soc/fsl/fsl_sai.h
> @@ -223,6 +223,32 @@ struct fsl_sai_soc_data {
> unsigned int reg_offset;
> };
>
> +/**
> + * struct fsl_sai_verid - version id data
> + * @major: major version number
> + * @minor: minor version number
> + * @feature: feature specification number
> + * 0000000000000000b - Standard feature set
> + * 0000000000000000b - Standard feature set
> + */
> +struct fsl_sai_verid {
> + u32 major;
> + u32 minor;
> + u32 feature;
> +};
> +
> +/**
> + * struct fsl_sai_param - parameter data
> + * @slot_num: The maximum number of slots per frame
> + * @fifo_depth: The number of words in each FIFO (depth)
> + * @dataline: The number of datalines implemented
> + */
> +struct fsl_sai_param {
> + u32 slot_num;
> + u32 fifo_depth;
> + u32 dataline;
> +};
> +
> struct fsl_sai {
> struct platform_device *pdev;
> struct regmap *regmap;
> @@ -243,6 +269,8 @@ struct fsl_sai {
> const struct fsl_sai_soc_data *soc_data;
> struct snd_dmaengine_dai_dma_data dma_params_rx;
> struct snd_dmaengine_dai_dma_data dma_params_tx;
> + struct fsl_sai_verid verid;
> + struct fsl_sai_param param;
> };
>
> #define TX 1
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] ASoC: fsl_sai: Set MCLK input or output direction
2020-09-16 10:16 [PATCH 0/3] ASoC: fsl_sai: update the register list Shengjiu Wang
2020-09-16 10:16 ` [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition Shengjiu Wang
2020-09-16 10:16 ` [PATCH 2/3] ASoC: fsl_sai: Add fsl_sai_check_version function Shengjiu Wang
@ 2020-09-16 10:16 ` Shengjiu Wang
2020-09-17 1:50 ` Nicolin Chen
2020-09-16 11:47 ` [PATCH 0/3] ASoC: fsl_sai: update the register list Fabio Estevam
3 siblings, 1 reply; 10+ messages in thread
From: Shengjiu Wang @ 2020-09-16 10:16 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, festevam, broonie, perex, tiwai,
alsa-devel, lgirdwood
Cc: linuxppc-dev, linux-kernel
SAI support select MCLK direction with version.major > 3
and version.minor > 1, the default direction is input,
set it to be output according to DT property.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 738b4dda7847..5117c1cd5682 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -1117,6 +1117,13 @@ static int fsl_sai_probe(struct platform_device *pdev)
if (ret < 0)
dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret);
+ /* Select MCLK direction */
+ if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
+ sai->verid.major >= 3 && sai->verid.minor >= 1) {
+ regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
+ FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
+ }
+
pm_runtime_enable(&pdev->dev);
regcache_cache_only(sai->regmap, true);
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 3/3] ASoC: fsl_sai: Set MCLK input or output direction
2020-09-16 10:16 ` [PATCH 3/3] ASoC: fsl_sai: Set MCLK input or output direction Shengjiu Wang
@ 2020-09-17 1:50 ` Nicolin Chen
0 siblings, 0 replies; 10+ messages in thread
From: Nicolin Chen @ 2020-09-17 1:50 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, timur, Xiubo.Lee, lgirdwood, linuxppc-dev, tiwai,
perex, broonie, festevam, linux-kernel
On Wed, Sep 16, 2020 at 06:16:27PM +0800, Shengjiu Wang wrote:
> SAI support select MCLK direction with version.major > 3
> and version.minor > 1, the default direction is input,
> set it to be output according to DT property.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> sound/soc/fsl/fsl_sai.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> index 738b4dda7847..5117c1cd5682 100644
> --- a/sound/soc/fsl/fsl_sai.c
> +++ b/sound/soc/fsl/fsl_sai.c
> @@ -1117,6 +1117,13 @@ static int fsl_sai_probe(struct platform_device *pdev)
> if (ret < 0)
> dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret);
>
> + /* Select MCLK direction */
> + if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
> + sai->verid.major >= 3 && sai->verid.minor >= 1) {
> + regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
> + FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
> + }
> +
> pm_runtime_enable(&pdev->dev);
> regcache_cache_only(sai->regmap, true);
>
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/3] ASoC: fsl_sai: update the register list
2020-09-16 10:16 [PATCH 0/3] ASoC: fsl_sai: update the register list Shengjiu Wang
` (2 preceding siblings ...)
2020-09-16 10:16 ` [PATCH 3/3] ASoC: fsl_sai: Set MCLK input or output direction Shengjiu Wang
@ 2020-09-16 11:47 ` Fabio Estevam
2020-09-16 11:51 ` Fabio Estevam
3 siblings, 1 reply; 10+ messages in thread
From: Fabio Estevam @ 2020-09-16 11:47 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, Timur Tabi, Xiubo.Lee, lgirdwood, tiwai, perex,
Nicolin Chen, broonie, linuxppc-dev, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 538 bytes --]
Knob kmg
On Wed, Sep 16, 2020, 07:23 Shengjiu Wang <shengjiu.wang@nxp.com> wrote:
> As sai ip is upgraded, so update sai register list.
>
> Shengjiu Wang (3):
> ASoC: fsl_sai: Add new added registers and new bit definition
> ASoC: fsl_sai: Add fsl_sai_check_version function
> ASoC: fsl_sai: Set MCLK input or output direction
>
> sound/soc/fsl/fsl_sai.c | 77 ++++++++++++++++++++++++++++++++++++
> sound/soc/fsl/fsl_sai.h | 87 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 164 insertions(+)
>
> --
> 2.27.0
>
>
[-- Attachment #2: Type: text/html, Size: 852 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 0/3] ASoC: fsl_sai: update the register list
2020-09-16 11:47 ` [PATCH 0/3] ASoC: fsl_sai: update the register list Fabio Estevam
@ 2020-09-16 11:51 ` Fabio Estevam
0 siblings, 0 replies; 10+ messages in thread
From: Fabio Estevam @ 2020-09-16 11:51 UTC (permalink / raw)
To: Shengjiu Wang
Cc: Linux-ALSA, Timur Tabi, Xiubo Li, Liam Girdwood, Takashi Iwai,
Jaroslav Kysela, Nicolin Chen, Mark Brown, linuxppc-dev,
linux-kernel
On Wed, Sep 16, 2020 at 8:47 AM Fabio Estevam <festevam@gmail.com> wrote:
>
> Knob kmg
Please ignore. It seems my cellphone wanted to write something.
^ permalink raw reply [flat|nested] 10+ messages in thread