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charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.120.23.2.4\)) Subject: Re: [PATCH 3/3] tools/perf: Add perf tools support to expose Performance Monitor Counter SPRs as part of extended regs From: Athira Rajeev In-Reply-To: <20210203162520.GG854763@kernel.org> Date: Thu, 4 Feb 2021 17:44:26 +0530 Content-Transfer-Encoding: quoted-printable Message-Id: References: <1612335337-1888-1-git-send-email-atrajeev@linux.vnet.ibm.com> <1612335337-1888-4-git-send-email-atrajeev@linux.vnet.ibm.com> <20210203162520.GG854763@kernel.org> To: Arnaldo Carvalho de Melo X-Mailer: Apple Mail (2.3608.120.23.2.4) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-02-04_06:2021-02-04, 2021-02-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 impostorscore=0 mlxscore=0 phishscore=0 priorityscore=1501 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2102040073 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kjain@linux.ibm.com, Madhavan Srinivasan , linuxppc-dev , jolsa@kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" > On 03-Feb-2021, at 9:55 PM, Arnaldo Carvalho de Melo = wrote: >=20 > Em Wed, Feb 03, 2021 at 01:55:37AM -0500, Athira Rajeev escreveu: >> To enable presenting of Performance Monitor Counter Registers >> (PMC1 to PMC6) as part of extended regsiters, patch adds these >> to sample_reg_mask in the tool side (to use with -I? option). >>=20 >> Simplified the PERF_REG_PMU_MASK_300/31 definition. Excluded the >> unsupported SPRs (MMCR3, SIER2, SIER3) from extended mask value for >> CPU_FTR_ARCH_300. >=20 > Applied just 3/3, the tooling part, to my local branch, please holler = if > I should wait a bit more. >=20 > - Arnaldo >=20 Thanks Arnaldo for taking the tool side changes. Athira. >> Signed-off-by: Athira Rajeev >> --- >> tools/arch/powerpc/include/uapi/asm/perf_regs.h | 28 = +++++++++++++++++++------ >> tools/perf/arch/powerpc/include/perf_regs.h | 6 ++++++ >> tools/perf/arch/powerpc/util/perf_regs.c | 6 ++++++ >> 3 files changed, 34 insertions(+), 6 deletions(-) >>=20 >> diff --git a/tools/arch/powerpc/include/uapi/asm/perf_regs.h = b/tools/arch/powerpc/include/uapi/asm/perf_regs.h >> index bdf5f10f8b9f..578b3ee86105 100644 >> --- a/tools/arch/powerpc/include/uapi/asm/perf_regs.h >> +++ b/tools/arch/powerpc/include/uapi/asm/perf_regs.h >> @@ -55,17 +55,33 @@ enum perf_event_powerpc_regs { >> PERF_REG_POWERPC_MMCR3, >> PERF_REG_POWERPC_SIER2, >> PERF_REG_POWERPC_SIER3, >> + PERF_REG_POWERPC_PMC1, >> + PERF_REG_POWERPC_PMC2, >> + PERF_REG_POWERPC_PMC3, >> + PERF_REG_POWERPC_PMC4, >> + PERF_REG_POWERPC_PMC5, >> + PERF_REG_POWERPC_PMC6, >> /* Max regs without the extended regs */ >> PERF_REG_POWERPC_MAX =3D PERF_REG_POWERPC_MMCRA + 1, >> }; >>=20 >> #define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) >>=20 >> -/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */ >> -#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + = 1)) - 1) - PERF_REG_PMU_MASK) >> -/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */ >> -#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + = 1)) - 1) - PERF_REG_PMU_MASK) >> +/* Exclude MMCR3, SIER2, SIER3 for CPU_FTR_ARCH_300 */ >> +#define PERF_EXCLUDE_REG_EXT_300 (7ULL << = PERF_REG_POWERPC_MMCR3) >>=20 >> -#define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1) >> -#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1) >> +/* >> + * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 >> + * includes 9 SPRS from MMCR0 to PMC6 excluding the >> + * unsupported SPRS in PERF_EXCLUDE_REG_EXT_300. >> + */ >> +#define PERF_REG_PMU_MASK_300 ((0xfffULL << = PERF_REG_POWERPC_MMCR0) - PERF_EXCLUDE_REG_EXT_300) >> + >> +/* >> + * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 >> + * includes 12 SPRs from MMCR0 to PMC6. >> + */ >> +#define PERF_REG_PMU_MASK_31 (0xfffULL << PERF_REG_POWERPC_MMCR0) >> + >> +#define PERF_REG_EXTENDED_MAX (PERF_REG_POWERPC_PMC6 + 1) >> #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ >> diff --git a/tools/perf/arch/powerpc/include/perf_regs.h = b/tools/perf/arch/powerpc/include/perf_regs.h >> index 63f3ac91049f..98b6f9eabfc3 100644 >> --- a/tools/perf/arch/powerpc/include/perf_regs.h >> +++ b/tools/perf/arch/powerpc/include/perf_regs.h >> @@ -71,6 +71,12 @@ >> [PERF_REG_POWERPC_MMCR3] =3D "mmcr3", >> [PERF_REG_POWERPC_SIER2] =3D "sier2", >> [PERF_REG_POWERPC_SIER3] =3D "sier3", >> + [PERF_REG_POWERPC_PMC1] =3D "pmc1", >> + [PERF_REG_POWERPC_PMC2] =3D "pmc2", >> + [PERF_REG_POWERPC_PMC3] =3D "pmc3", >> + [PERF_REG_POWERPC_PMC4] =3D "pmc4", >> + [PERF_REG_POWERPC_PMC5] =3D "pmc5", >> + [PERF_REG_POWERPC_PMC6] =3D "pmc6", >> }; >>=20 >> static inline const char *perf_reg_name(int id) >> diff --git a/tools/perf/arch/powerpc/util/perf_regs.c = b/tools/perf/arch/powerpc/util/perf_regs.c >> index 2b6d4704e3aa..8116a253f91f 100644 >> --- a/tools/perf/arch/powerpc/util/perf_regs.c >> +++ b/tools/perf/arch/powerpc/util/perf_regs.c >> @@ -68,6 +68,12 @@ >> SMPL_REG(mmcr3, PERF_REG_POWERPC_MMCR3), >> SMPL_REG(sier2, PERF_REG_POWERPC_SIER2), >> SMPL_REG(sier3, PERF_REG_POWERPC_SIER3), >> + SMPL_REG(pmc1, PERF_REG_POWERPC_PMC1), >> + SMPL_REG(pmc2, PERF_REG_POWERPC_PMC2), >> + SMPL_REG(pmc3, PERF_REG_POWERPC_PMC3), >> + SMPL_REG(pmc4, PERF_REG_POWERPC_PMC4), >> + SMPL_REG(pmc5, PERF_REG_POWERPC_PMC5), >> + SMPL_REG(pmc6, PERF_REG_POWERPC_PMC6), >> SMPL_REG_END >> }; >>=20 >> --=20 >> 1.8.3.1 >>=20 >=20 > --=20 >=20 > - Arnaldo