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[118.208.203.28]) by smtp.gmail.com with ESMTPSA id 20-20020a631154000000b0041d6d37deb5sm220797pgr.81.2022.09.19.20.52.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Sep 2022 20:52:05 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 20 Sep 2022 13:51:59 +1000 Message-Id: Subject: Re: [PACTH v2] powerpc/pseries/mce: Avoid instrumentation in realmode From: "Nicholas Piggin" To: "Ganesh" , , X-Mailer: aerc 0.11.0 References: <20220905063811.16454-1-ganeshgr@linux.ibm.com> <895f4387-582a-6d60-a176-e2112f506e12@linux.ibm.com> In-Reply-To: <895f4387-582a-6d60-a176-e2112f506e12@linux.ibm.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mahesh@linux.ibm.com, sachinp@linux.ibm.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon Sep 19, 2022 at 4:03 PM AEST, Ganesh wrote: > On 9/7/22 09:49, Nicholas Piggin wrote: > > > On Mon Sep 5, 2022 at 4:38 PM AEST, Ganesh Goudar wrote: > >> Part of machine check error handling is done in realmode, > >> As of now instrumentation is not possible for any code that > >> runs in realmode. > >> When MCE is injected on KASAN enabled kernel, crash is > >> observed, Hence force inline or mark no instrumentation > >> for functions which can run in realmode, to avoid KASAN > >> instrumentation. > >> > >> Signed-off-by: Ganesh Goudar > >> --- > >> v2: Force inline few more functions. > >> --- > >> arch/powerpc/include/asm/hw_irq.h | 8 ++++---- > >> arch/powerpc/include/asm/interrupt.h | 2 +- > >> arch/powerpc/include/asm/rtas.h | 4 ++-- > >> arch/powerpc/kernel/rtas.c | 4 ++-- > >> 4 files changed, 9 insertions(+), 9 deletions(-) > >> > >> diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/= asm/hw_irq.h > >> index 26ede09c521d..3264991fe524 100644 > >> --- a/arch/powerpc/include/asm/hw_irq.h > >> +++ b/arch/powerpc/include/asm/hw_irq.h > >> @@ -111,7 +111,7 @@ static inline void __hard_RI_enable(void) > >> #ifdef CONFIG_PPC64 > >> #include > >> =20 > >> -static inline notrace unsigned long irq_soft_mask_return(void) > >> +static __always_inline notrace unsigned long irq_soft_mask_return(voi= d) > >> { > >> return READ_ONCE(local_paca->irq_soft_mask); > >> } > >> @@ -121,7 +121,7 @@ static inline notrace unsigned long irq_soft_mask_= return(void) > >> * for the critical section and as a clobber because > >> * we changed paca->irq_soft_mask > >> */ > >> -static inline notrace void irq_soft_mask_set(unsigned long mask) > >> +static __always_inline notrace void irq_soft_mask_set(unsigned long m= ask) > >> { > >> /* > >> * The irq mask must always include the STD bit if any are set. > > This doesn't give a reason why it's __always_inline, and having the > > notrace attribute makes it possibly confusing. I think it would be easy > > for someone to break without realising. Could you add a noinstr to thes= e > > instead / as well? > > Yeah we can add noinstr. Missed to see your comment, Sorry for the delaye= d reply Okay that would be good. I would prefer to avoid changing the inline-ness of things in a fix patch if possible. > > > > > What about adding a 'realmode' function annotation that includes noinst= r? > > You mean to define a new function annotation? Yes, a powerpc specific one that has the necessary adjustments. I think it would be helpful documentation for the code and possibly something we could use to do additional debug checking with at some point too. Thanks, Nick