From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0135.outbound.protection.outlook.com [65.55.169.135]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id E9FAE1A03E9 for ; Wed, 1 Oct 2014 06:35:17 +1000 (EST) From: Jojy Varghese To: Scott Wood Subject: Re: [PATCH] powerpc/fsl: Add support for pci(e) machine check exception on E500MC / E5500 Date: Tue, 30 Sep 2014 20:20:03 +0000 Message-ID: In-Reply-To: <1412108227.13320.309.camel@snotra.buserror.net> Content-Type: text/plain; charset="iso-8859-1" MIME-Version: 1.0 Cc: "hongtao.jia@freescale.com" , "linux-kernel@vger.kernel.org" , Guenter Roeck , Paul Mackerras , "linuxppc-dev@lists.ozlabs.org" , Guenter Roeck List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 9/30/14 1:17 PM, "Scott Wood" wrote: >On Tue, 2014-09-30 at 20:15 +0000, Jojy Varghese wrote: >>=20 >> On 9/30/14 8:50 AM, "Guenter Roeck" wrote: >>=20 >> >On Mon, Sep 29, 2014 at 06:31:06PM -0500, Scott Wood wrote: >> >> Which specific chip and revision did you see this on? What is the >>value >> >> in MCSR? >> >>=20 >> >Jojy can answer that, at least for P5020. We have seen it on P5040 as >> >well, >> >though, so it is not just limited to one chip/revision. >>=20 >> The specifics are: >> PVR: 0x80240012 >> Instruction that causes the MC exception: lwbrx >> The faulty load address is also present in RB. So we could change the >> logic to use that >> instead of DEAR. What I don=B9t know is of there are other cases also >>which >> escapes the current logic. > >Could you find out what MCSR was when that happened? I'm most >interested in whether MAV was set, but the other bits would be >interesting as well. MCSR=3Da000 ( Load Error Report) > >-Scott > > Thanks Jojy