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From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Shivaprasad G Bhat" <sbhat@linux.ibm.com>, <kvm@vger.kernel.org>,
	<linux-doc@vger.kernel.org>, <linuxppc-dev@lists.ozlabs.org>
Cc: atrajeev@linux.vnet.ibm.com, corbet@lwn.net,
	linux-kernel@vger.kernel.org, namhyung@kernel.org,
	naveen.n.rao@linux.ibm.com, pbonzini@redhat.com,
	jniethe5@gmail.com
Subject: Re: [PATCH 4/6] KVM: PPC: Book3S HV: Add one-reg interface for DEXCR register
Date: Tue, 04 Jun 2024 15:43:06 +1000	[thread overview]
Message-ID: <D1QZRTRK2WWI.20TJKC3RK1K9C@gmail.com> (raw)
In-Reply-To: <171741327891.6631.10339033341166150910.stgit@linux.ibm.com>

On Mon Jun 3, 2024 at 9:14 PM AEST, Shivaprasad G Bhat wrote:
> The patch adds a one-reg register identifier which can be used to
> read and set the DEXCR for the guest during enter/exit with
> KVM_REG_PPC_DEXCR. The specific SPR KVM API documentation
> too updated.

I wonder if the uapi and documentation parts should go in their
own patch in a ppc kvm uapi topic branch? Otherwise looks okay.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>

>
> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
> ---
>  Documentation/virt/kvm/api.rst            |    1 +
>  arch/powerpc/include/uapi/asm/kvm.h       |    1 +
>  arch/powerpc/kvm/book3s_hv.c              |    6 ++++++
>  tools/arch/powerpc/include/uapi/asm/kvm.h |    1 +
>  4 files changed, 9 insertions(+)
>
> diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst
> index a71d91978d9e..81077c654281 100644
> --- a/Documentation/virt/kvm/api.rst
> +++ b/Documentation/virt/kvm/api.rst
> @@ -2441,6 +2441,7 @@ registers, find a list below:
>    PPC     KVM_REG_PPC_PTCR                64
>    PPC     KVM_REG_PPC_DAWR1               64
>    PPC     KVM_REG_PPC_DAWRX1              64
> +  PPC     KVM_REG_PPC_DEXCR               64
>    PPC     KVM_REG_PPC_TM_GPR0             64
>    ...
>    PPC     KVM_REG_PPC_TM_GPR31            64
> diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
> index 1691297a766a..fcb947f65667 100644
> --- a/arch/powerpc/include/uapi/asm/kvm.h
> +++ b/arch/powerpc/include/uapi/asm/kvm.h
> @@ -645,6 +645,7 @@ struct kvm_ppc_cpu_char {
>  #define KVM_REG_PPC_SIER3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
>  #define KVM_REG_PPC_DAWR1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
>  #define KVM_REG_PPC_DAWRX1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
> +#define KVM_REG_PPC_DEXCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6)
>  
>  /* Transactional Memory checkpointed state:
>   * This is all GPRs, all VSX regs and a subset of SPRs
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index b576781d58d5..1294c6839d37 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -2349,6 +2349,9 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
>  	case KVM_REG_PPC_DAWRX1:
>  		*val = get_reg_val(id, kvmppc_get_dawrx1_hv(vcpu));
>  		break;
> +	case KVM_REG_PPC_DEXCR:
> +		*val = get_reg_val(id, kvmppc_get_dexcr_hv(vcpu));
> +		break;
>  	case KVM_REG_PPC_CIABR:
>  		*val = get_reg_val(id, kvmppc_get_ciabr_hv(vcpu));
>  		break;
> @@ -2592,6 +2595,9 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
>  	case KVM_REG_PPC_DAWRX1:
>  		kvmppc_set_dawrx1_hv(vcpu, set_reg_val(id, *val) & ~DAWRX_HYP);
>  		break;
> +	case KVM_REG_PPC_DEXCR:
> +		kvmppc_set_dexcr_hv(vcpu, set_reg_val(id, *val));
> +		break;
>  	case KVM_REG_PPC_CIABR:
>  		kvmppc_set_ciabr_hv(vcpu, set_reg_val(id, *val));
>  		/* Don't allow setting breakpoints in hypervisor code */
> diff --git a/tools/arch/powerpc/include/uapi/asm/kvm.h b/tools/arch/powerpc/include/uapi/asm/kvm.h
> index 1691297a766a..fcb947f65667 100644
> --- a/tools/arch/powerpc/include/uapi/asm/kvm.h
> +++ b/tools/arch/powerpc/include/uapi/asm/kvm.h
> @@ -645,6 +645,7 @@ struct kvm_ppc_cpu_char {
>  #define KVM_REG_PPC_SIER3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
>  #define KVM_REG_PPC_DAWR1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
>  #define KVM_REG_PPC_DAWRX1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
> +#define KVM_REG_PPC_DEXCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6)
>  
>  /* Transactional Memory checkpointed state:
>   * This is all GPRs, all VSX regs and a subset of SPRs


  reply	other threads:[~2024-06-04  5:44 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-03 11:13 [PATCH 0/6] KVM: PPC: Book3S HV: Nested guest migration fixes Shivaprasad G Bhat
2024-06-03 11:14 ` [PATCH 1/6] KVM: PPC: Book3S HV: Fix the set_one_reg for MMCR3 Shivaprasad G Bhat
2024-06-03 11:14 ` [PATCH 2/6] KVM: PPC: Book3S HV: Fix the get_one_reg of SDAR Shivaprasad G Bhat
2024-06-03 11:14 ` [PATCH 3/6] KVM: PPC: Book3S HV nestedv2: Keep nested guest DEXCR in sync Shivaprasad G Bhat
2024-06-04  5:46   ` Nicholas Piggin
2024-06-03 11:14 ` [PATCH 4/6] KVM: PPC: Book3S HV: Add one-reg interface for DEXCR register Shivaprasad G Bhat
2024-06-04  5:43   ` Nicholas Piggin [this message]
2024-06-04 11:29     ` Michael Ellerman
2024-06-04 11:26   ` Michael Ellerman
2024-06-03 11:14 ` [PATCH 5/6] KVM: PPC: Book3S HV nestedv2: Keep nested guest HASHKEYR in sync Shivaprasad G Bhat
2024-06-04  5:46   ` Nicholas Piggin
2024-06-03 11:15 ` [PATCH 6/6] KVM: PPC: Book3S HV: Add one-reg interface for HASHKEYR register Shivaprasad G Bhat
2024-06-04  5:43   ` Nicholas Piggin
2024-06-04  6:07   ` Nicholas Piggin
2024-06-05 13:13     ` Shivaprasad G Bhat
2024-06-04  5:48 ` [PATCH 0/6] KVM: PPC: Book3S HV: Nested guest migration fixes Nicholas Piggin

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