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AJvYcCVsJquR1Bog4t2GEp5uB9xzaVShVkuEnNcd8PZRQqOH6ymSjMI25pWlOCXfVg/pFHGVGWkvsVCaBxaMkayDLNxLUajVagh/F//9++Y7Mw== X-Gm-Message-State: AOJu0YwCdxPBI/c+JL3M/ZX1Tm6VxJLqphNwq69mOlLrbIcrVih36Cc4 BhACTxOkSZVpVCqwJIF/Gwqu2bbSL2nqIh/W4fPYhah0KRI9XaJz X-Google-Smtp-Source: AGHT+IHdULvM/UoX71VpmSro0BVG2S25hAJs5rPoN0XzL1Vuyeuwb3p6V/lc/pV9Udr55ns8zfQHzw== X-Received: by 2002:a17:902:d2d2:b0:1f6:857b:b5c with SMTP id d9443c01a7336-1f6857b4df3mr34853835ad.32.1717479794361; Mon, 03 Jun 2024 22:43:14 -0700 (PDT) Received: from localhost ([1.146.11.115]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f683d1a770sm21936025ad.13.2024.06.03.22.43.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Jun 2024 22:43:14 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 04 Jun 2024 15:43:06 +1000 Message-Id: Subject: Re: [PATCH 4/6] KVM: PPC: Book3S HV: Add one-reg interface for DEXCR register From: "Nicholas Piggin" To: "Shivaprasad G Bhat" , , , X-Mailer: aerc 0.17.0 References: <171741323521.6631.11242552089199677395.stgit@linux.ibm.com> <171741327891.6631.10339033341166150910.stgit@linux.ibm.com> In-Reply-To: <171741327891.6631.10339033341166150910.stgit@linux.ibm.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, corbet@lwn.net, linux-kernel@vger.kernel.org, namhyung@kernel.org, naveen.n.rao@linux.ibm.com, pbonzini@redhat.com, jniethe5@gmail.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon Jun 3, 2024 at 9:14 PM AEST, Shivaprasad G Bhat wrote: > The patch adds a one-reg register identifier which can be used to > read and set the DEXCR for the guest during enter/exit with > KVM_REG_PPC_DEXCR. The specific SPR KVM API documentation > too updated. I wonder if the uapi and documentation parts should go in their own patch in a ppc kvm uapi topic branch? Otherwise looks okay. Reviewed-by: Nicholas Piggin > > Signed-off-by: Shivaprasad G Bhat > --- > Documentation/virt/kvm/api.rst | 1 + > arch/powerpc/include/uapi/asm/kvm.h | 1 + > arch/powerpc/kvm/book3s_hv.c | 6 ++++++ > tools/arch/powerpc/include/uapi/asm/kvm.h | 1 + > 4 files changed, 9 insertions(+) > > diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.= rst > index a71d91978d9e..81077c654281 100644 > --- a/Documentation/virt/kvm/api.rst > +++ b/Documentation/virt/kvm/api.rst > @@ -2441,6 +2441,7 @@ registers, find a list below: > PPC KVM_REG_PPC_PTCR 64 > PPC KVM_REG_PPC_DAWR1 64 > PPC KVM_REG_PPC_DAWRX1 64 > + PPC KVM_REG_PPC_DEXCR 64 > PPC KVM_REG_PPC_TM_GPR0 64 > ... > PPC KVM_REG_PPC_TM_GPR31 64 > diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/u= api/asm/kvm.h > index 1691297a766a..fcb947f65667 100644 > --- a/arch/powerpc/include/uapi/asm/kvm.h > +++ b/arch/powerpc/include/uapi/asm/kvm.h > @@ -645,6 +645,7 @@ struct kvm_ppc_cpu_char { > #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) > #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4) > #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5) > +#define KVM_REG_PPC_DEXCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6) > =20 > /* Transactional Memory checkpointed state: > * This is all GPRs, all VSX regs and a subset of SPRs > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index b576781d58d5..1294c6839d37 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -2349,6 +2349,9 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *v= cpu, u64 id, > case KVM_REG_PPC_DAWRX1: > *val =3D get_reg_val(id, kvmppc_get_dawrx1_hv(vcpu)); > break; > + case KVM_REG_PPC_DEXCR: > + *val =3D get_reg_val(id, kvmppc_get_dexcr_hv(vcpu)); > + break; > case KVM_REG_PPC_CIABR: > *val =3D get_reg_val(id, kvmppc_get_ciabr_hv(vcpu)); > break; > @@ -2592,6 +2595,9 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *v= cpu, u64 id, > case KVM_REG_PPC_DAWRX1: > kvmppc_set_dawrx1_hv(vcpu, set_reg_val(id, *val) & ~DAWRX_HYP); > break; > + case KVM_REG_PPC_DEXCR: > + kvmppc_set_dexcr_hv(vcpu, set_reg_val(id, *val)); > + break; > case KVM_REG_PPC_CIABR: > kvmppc_set_ciabr_hv(vcpu, set_reg_val(id, *val)); > /* Don't allow setting breakpoints in hypervisor code */ > diff --git a/tools/arch/powerpc/include/uapi/asm/kvm.h b/tools/arch/power= pc/include/uapi/asm/kvm.h > index 1691297a766a..fcb947f65667 100644 > --- a/tools/arch/powerpc/include/uapi/asm/kvm.h > +++ b/tools/arch/powerpc/include/uapi/asm/kvm.h > @@ -645,6 +645,7 @@ struct kvm_ppc_cpu_char { > #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) > #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4) > #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5) > +#define KVM_REG_PPC_DEXCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6) > =20 > /* Transactional Memory checkpointed state: > * This is all GPRs, all VSX regs and a subset of SPRs