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From: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: [Cbe-oss-dev] Cell and new CPU feature bits
Date: Fri, 19 May 2006 09:49:18 +0200
To: Andrew Pinski <pinskia@physics.uc.edu>
Cc: Olof Johansson <olof@lixom.net>,
	linuxppc-dev list <linuxppc-dev@ozlabs.org>,
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>> I'm assuming you mean the instructions described under "AltiVec  
>> Memory
>> Bandwidth Management" in secion 5.2 of the Altivec PEM -- dst, dstt,
>> dstst, dss and dssall?
>
> They are nops on the Cell though.

And that is a compliant implementation.  I don't see a need
or real use for a feature bit here, esp. if we do get one for
the extended dcbt insns (which often are used as a replacement
for the data streaming insns).

> They are also microcoded on the 970.

No, they are cracked, instead.  Much lower hit.  They are completion
serialized though, so the only insn in an issue group, etc.


Segher