From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 3EECBDDEC9 for ; Thu, 7 Jun 2007 16:48:29 +1000 (EST) In-Reply-To: <1181186378.10296.41.camel@localhost.localdomain> References: <1181186378.10296.41.camel@localhost.localdomain> Mime-Version: 1.0 (Apple Message framework v752.2) Content-Type: text/plain; charset=US-ASCII; delsp=yes; format=flowed Message-Id: From: Kumar Gala Subject: Re: [PATCH]: Add 8548 pcie bus number workaround Date: Thu, 7 Jun 2007 01:48:40 -0500 To: Zang Roy-r61911 Cc: linuxppc-dev list , Paul Mackerras List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Jun 6, 2007, at 10:19 PM, Zang Roy-r61911 wrote: > > From: Zang Roy-r61911 > > Remove legacy pcie support for 8641 chip. > General PCI code can fully support 8641 Rev2.0 chip. > For 8548 PEX controller, PCIE host controller configure > space can only be accessed as "bus->number = 0" in > the PCI architecture. So "bus->number == hose->bus_offset" > judgment is added. Uugh, I'm completely confused. Does 8548 rev 2.x have some errata (or 'feature') that 8641 doesn't have? - k