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Sat, 14 Aug 2021 07:12:05 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 26F67AE057; Sat, 14 Aug 2021 07:12:05 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3E6AFAE055; Sat, 14 Aug 2021 07:12:04 +0000 (GMT) Received: from smtpclient.apple (unknown [9.195.35.224]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Sat, 14 Aug 2021 07:12:04 +0000 (GMT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [PATCH v1 17/55] KVM: PPC: Book3S HV P9: Implement PMU save/restore in C From: Athira Rajeev In-Reply-To: <1628827731.ai2zz7xxwa.astroid@bobo.none> Date: Sat, 14 Aug 2021 12:42:01 +0530 Content-Transfer-Encoding: quoted-printable Message-Id: References: <20210726035036.739609-1-npiggin@gmail.com> <20210726035036.739609-18-npiggin@gmail.com> <1A47BBEF-FC8C-4C4D-8393-9DE66B7FF96C@linux.vnet.ibm.com> <1628827731.ai2zz7xxwa.astroid@bobo.none> To: Nicholas Piggin X-Mailer: Apple Mail (2.3654.120.0.1.13) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: M3RjjLXOy9ce4iclpcjtXKG439Fer_9d X-Proofpoint-GUID: 4lr-HUtG9oFOCdUXeDgAGrWBx8L4YOkc X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-14_02:2021-08-13, 2021-08-14 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=993 malwarescore=0 bulkscore=0 impostorscore=0 phishscore=0 priorityscore=1501 spamscore=0 mlxscore=0 adultscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108140043 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" > On 13-Aug-2021, at 9:54 AM, Nicholas Piggin wrote: >=20 > Excerpts from Athira Rajeev's message of August 9, 2021 1:03 pm: >>=20 >>=20 >>> On 26-Jul-2021, at 9:19 AM, Nicholas Piggin = wrote: >=20 >=20 >>> +static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra) >>> +{ >>> + if (!(mmcr0 & MMCR0_FC)) >>> + goto do_freeze; >>> + if (mmcra & MMCRA_SAMPLE_ENABLE) >>> + goto do_freeze; >>> + if (cpu_has_feature(CPU_FTR_ARCH_31)) { >>> + if (!(mmcr0 & MMCR0_PMCCEXT)) >>> + goto do_freeze; >>> + if (!(mmcra & MMCRA_BHRB_DISABLE)) >>> + goto do_freeze; >>> + } >>> + return; >>> + >>> +do_freeze: >>> + mmcr0 =3D MMCR0_FC; >>> + mmcra =3D 0; >>> + if (cpu_has_feature(CPU_FTR_ARCH_31)) { >>> + mmcr0 |=3D MMCR0_PMCCEXT; >>> + mmcra =3D MMCRA_BHRB_DISABLE; >>> + } >>> + >>> + mtspr(SPRN_MMCR0, mmcr0); >>> + mtspr(SPRN_MMCRA, mmcra); >>> + isync(); >>> +} >>> + >> Hi Nick, >>=20 >> After feezing pmu, do we need to clear =E2=80=9Cpmcregs_in_use=E2=80=9D= as well? >=20 > Not until we save the values out of the registers. pmcregs_in_use =3D = 0=20 > means our hypervisor is free to clear our PMU register contents. >=20 >> Also can=E2=80=99t we unconditionally do the MMCR0/MMCRA/ freeze = settings in here ? do we need the if conditions for FC/PMCCEXT/BHRB ? >=20 > I think it's possible, but pretty minimal advantage. I would prefer to=20= > set them the way perf does for now. Sure Nick,=20 Other changes looks good to me. Reviewed-by: Athira Rajeev Thanks Athira > If we can move this code into perf/ > it should become easier for you to tweak things. >=20 > Thanks, > Nick