RE: New MPC5200 Eratta/ATA Bugs

["Stephen Warren" <SWarren@nvidia.com>]

Eric N. Johnson (ACD) wrote:
> Freescale just realeased a new version of the eratta (hardware bugs)=20
> document for the MPC5200.  It was posted last week, and adds some
pretty=20
> significant problems to the FEC Ethernet and IDE/ATA sections.
>
> Specifically, I'm wonder if Eratta ID 485 may be the cause of some of
the=20
> IDE issues we've been attributing to Bestcomm:
>=20
>   "During the concurrent access of ATA DMA READ and PCI or LPC the
>    ATA_ISOLATION signal can be incorrectly driven when ATA is paused."
>=20
> Unfortunately, their proposed workaround isn't appropriate for many=20
> cases.  They suggest that you not use "ATA_ISOLATION" and connect the
ATA=20
> device directly to the LP bus without any buffering.  This could lead
to=20
> serious bus integrity issues, especially if the ATA device is
connected by=20
> a ribbon cable.=20

Freescale certainly confirmed that was the issue we were up against.

Freescale have been working with us on a board work-around for the
problem. This basically involves deriving a substitute ATA_ISOLATION
signal from the regular ATA control signals, in some cases.

--=20
Stephen Warren, Software Engineer, NVIDIA, Fort Collins, CO
swarren@nvidia.com        http://www.nvidia.com/
swarren@wwwdotorg.org     http://www.wwwdotorg.org/pgp.html