[PATCH 0/13] Hugetlb for 64-bit Freescale Book3E

[PATCH 0/13] Hugetlb for 64-bit Freescale Book3E

[Becky Bruce]

This series of patches contains mostly cleanup code that allows
the enablement of hugetlb for 64-bit Freescale BookE processors.
There are also some bits that I dropped from the 32-bit release
that are added back, as they are needed by other implementations.
Otherwise, it's mostly a bunch of code rearrangement, changes
in #include protections, and Kconfig changes.

Cheers,
Becky

 arch/powerpc/configs/corenet32_smp_defconfig |    9 +--
 arch/powerpc/configs/corenet64_smp_defconfig |    6 +-
 arch/powerpc/configs/mpc85xx_defconfig       |    6 +-
 arch/powerpc/configs/mpc85xx_smp_defconfig   |    7 +-
 arch/powerpc/include/asm/hugetlb.h           |   36 ++++++--
 arch/powerpc/include/asm/page_64.h           |    2 +
 arch/powerpc/kernel/setup_64.c               |   10 ++
 arch/powerpc/mm/hugetlbpage-book3e.c         |   15 ++--
 arch/powerpc/mm/hugetlbpage.c                |  116 ++++++++++++++++----------
 arch/powerpc/mm/tlb_low_64e.S                |   36 ++++-----
 arch/powerpc/mm/tlb_nohash.c                 |    2 +-
 arch/powerpc/platforms/Kconfig.cputype       |    4 +-
 12 files changed, 143 insertions(+), 106 deletions(-)

[PATCH 01/13] powerpc: Only define HAVE_ARCH_HUGETLB_UNMAPPED_AREA if PPC_MM_SLICES

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

If we don't have slices, we should be able to use the generic
hugetlb_get_unmapped_area() code

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/include/asm/page_64.h |    2 ++
 arch/powerpc/mm/hugetlbpage.c      |    6 ++----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fb40ede..fed85e6 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -130,7 +130,9 @@ do {						\
 
 #ifdef CONFIG_HUGETLB_PAGE
 
+#ifdef CONFIG_PPC_MM_SLICES
 #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
+#endif
 
 #endif /* !CONFIG_HUGETLB_PAGE */
 
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 48b65be..71c6533 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -686,19 +686,17 @@ int gup_hugepd(hugepd_t *hugepd, unsigned pdshift,
 	return 1;
 }
 
+#ifdef CONFIG_PPC_MM_SLICES
 unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
 					unsigned long len, unsigned long pgoff,
 					unsigned long flags)
 {
-#ifdef CONFIG_PPC_MM_SLICES
 	struct hstate *hstate = hstate_file(file);
 	int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
 
 	return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0);
-#else
-	return get_unmapped_area(file, addr, len, pgoff, flags);
-#endif
 }
+#endif
 
 unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
 {
-- 
1.5.6.5

[PATCH 02/13] powerpc: hugetlb: fix huge_ptep_set_access_flags return value

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

There was an unconditional return of "1" in the original code
from David Gibson, and I dropped it because it wasn't needed
for FSL BOOKE 32-bit.  However, not all systems (including 64-bit
FSL BOOKE) do loading of the hpte from the fault handler asm
and depend on this function returning 1, which causes a call
to update_mmu_cache() that writes an entry into the tlb.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 arch/powerpc/include/asm/hugetlb.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 8600493..70f9885 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -124,7 +124,18 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
 					     unsigned long addr, pte_t *ptep,
 					     pte_t pte, int dirty)
 {
+#if defined(CONFIG_PPC_MMU_NOHASH) && \
+	!(defined(CONFIG_PPC_FSL_BOOK3E) && defined(CONFIG_PPC32))
+	/*
+	 * The "return 1" forces a call of update_mmu_cache, which will write a
+	 * TLB entry.  Without this, platforms that don't do a write of the TLB
+	 * entry in the TLB miss handler asm will fault ad infinitum.
+	 */
+	ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+	return 1;
+#else
 	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+#endif
 }
 
 static inline pte_t huge_ptep_get(pte_t *ptep)
-- 
1.5.6.5

[PATCH 03/13] powerpc: Fix booke hugetlb preload code for PPC_MM_SLICES and 64-bit

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

This patch does 2 things: It corrects the code that determines the
size to write into MAS1 for the PPC_MM_SLICES case (this originally
came from David Gibson and I had incorrectly altered it), and it
changes the methodolody used to calculate the size for !PPC_MM_SLICES
to work for 64-bit as well as 32-bit.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 arch/powerpc/mm/hugetlbpage-book3e.c |   15 ++++++---------
 1 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c
index 343ad0b..4d6d849 100644
--- a/arch/powerpc/mm/hugetlbpage-book3e.c
+++ b/arch/powerpc/mm/hugetlbpage-book3e.c
@@ -45,23 +45,20 @@ void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte)
 	unsigned long flags;
 
 #ifdef CONFIG_PPC_FSL_BOOK3E
-	int index, lz, ncams;
-	struct vm_area_struct *vma;
+	int index, ncams;
 #endif
 
 	if (unlikely(is_kernel_addr(ea)))
 		return;
 
 #ifdef CONFIG_PPC_MM_SLICES
-	psize = mmu_get_tsize(get_slice_psize(mm, ea));
-	tsize = mmu_get_psize(psize);
+	psize = get_slice_psize(mm, ea);
+	tsize = mmu_get_tsize(psize);
 	shift = mmu_psize_defs[psize].shift;
 #else
-	vma = find_vma(mm, ea);
-	psize = vma_mmu_pagesize(vma);	/* returns actual size in bytes */
-	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (psize));
-	shift = 31 - lz;
-	tsize = 21 - lz;
+	psize = vma_mmu_pagesize(find_vma(mm, ea));
+	shift = __ilog2(psize);
+	tsize = shift - 10;
 #endif
 
 	/*
-- 
1.5.6.5

[PATCH 04/13] powerpc: Update hugetlb huge_pte_alloc and tablewalk code for FSL BOOKE

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

This updates the hugetlb page table code to handle 64-bit FSL_BOOKE.
The previous 32-bit work counted on the inner levels of the page table
collapsing.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/mm/hugetlbpage.c |   48 +++++++++++++++++++++++++++++++++++-----
 1 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 71c6533..b4a4884 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -155,11 +155,28 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
 			hpdp->pd = 0;
 		kmem_cache_free(cachep, new);
 	}
+#else
+	if (!hugepd_none(*hpdp))
+		kmem_cache_free(cachep, new);
+	else
+		hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
 #endif
 	spin_unlock(&mm->page_table_lock);
 	return 0;
 }
 
+/*
+ * These macros define how to determine which level of the page table holds
+ * the hpdp.
+ */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+#define HUGEPD_PGD_SHIFT PGDIR_SHIFT
+#define HUGEPD_PUD_SHIFT PUD_SHIFT
+#else
+#define HUGEPD_PGD_SHIFT PUD_SHIFT
+#define HUGEPD_PUD_SHIFT PMD_SHIFT
+#endif
+
 pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
 {
 	pgd_t *pg;
@@ -172,12 +189,13 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz
 	addr &= ~(sz-1);
 
 	pg = pgd_offset(mm, addr);
-	if (pshift >= PUD_SHIFT) {
+
+	if (pshift >= HUGEPD_PGD_SHIFT) {
 		hpdp = (hugepd_t *)pg;
 	} else {
 		pdshift = PUD_SHIFT;
 		pu = pud_alloc(mm, pg, addr);
-		if (pshift >= PMD_SHIFT) {
+		if (pshift >= HUGEPD_PUD_SHIFT) {
 			hpdp = (hugepd_t *)pu;
 		} else {
 			pdshift = PMD_SHIFT;
@@ -453,14 +471,23 @@ static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
 	unsigned long start;
 
 	start = addr;
-	pmd = pmd_offset(pud, addr);
 	do {
+		pmd = pmd_offset(pud, addr);
 		next = pmd_addr_end(addr, end);
 		if (pmd_none(*pmd))
 			continue;
+#ifdef CONFIG_PPC_FSL_BOOK3E
+		/*
+		 * Increment next by the size of the huge mapping since
+		 * there may be more than one entry at this level for a
+		 * single hugepage, but all of them point to
+		 * the same kmem cache that holds the hugepte.
+		 */
+		next = addr + (1 << hugepd_shift(*(hugepd_t *)pmd));
+#endif
 		free_hugepd_range(tlb, (hugepd_t *)pmd, PMD_SHIFT,
 				  addr, next, floor, ceiling);
-	} while (pmd++, addr = next, addr != end);
+	} while (addr = next, addr != end);
 
 	start &= PUD_MASK;
 	if (start < floor)
@@ -487,8 +514,8 @@ static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd,
 	unsigned long start;
 
 	start = addr;
-	pud = pud_offset(pgd, addr);
 	do {
+		pud = pud_offset(pgd, addr);
 		next = pud_addr_end(addr, end);
 		if (!is_hugepd(pud)) {
 			if (pud_none_or_clear_bad(pud))
@@ -496,10 +523,19 @@ static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd,
 			hugetlb_free_pmd_range(tlb, pud, addr, next, floor,
 					       ceiling);
 		} else {
+#ifdef CONFIG_PPC_FSL_BOOK3E
+			/*
+			 * Increment next by the size of the huge mapping since
+			 * there may be more than one entry at this level for a
+			 * single hugepage, but all of them point to
+			 * the same kmem cache that holds the hugepte.
+			 */
+			next = addr + (1 << hugepd_shift(*(hugepd_t *)pud));
+#endif
 			free_hugepd_range(tlb, (hugepd_t *)pud, PUD_SHIFT,
 					  addr, next, floor, ceiling);
 		}
-	} while (pud++, addr = next, addr != end);
+	} while (addr = next, addr != end);
 
 	start &= PGDIR_MASK;
 	if (start < floor)
-- 
1.5.6.5

[PATCH 05/13] powerpc: hugetlb: modify include usage for FSL BookE code

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

The original 32-bit hugetlb implementation used PPC64 vs PPC32 to
determine which code path to take.  However, the final hugetlb
implementation for 64-bit FSL ended up shared with the FSL
32-bit code so the actual check needs to be FSL_BOOK3E vs
everything else.  This patch changes the include protections to
reflect this.

There are also a couple of related comment fixes.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/include/asm/hugetlb.h |    6 ++--
 arch/powerpc/mm/hugetlbpage.c      |   54 ++++++++++++++++-------------------
 arch/powerpc/mm/tlb_nohash.c       |    2 +-
 3 files changed, 29 insertions(+), 33 deletions(-)

diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 70f9885..273acfa 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -22,14 +22,14 @@ static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
 				    unsigned pdshift)
 {
 	/*
-	 * On 32-bit, we have multiple higher-level table entries that point to
-	 * the same hugepte.  Just use the first one since they're all
+	 * On FSL BookE, we have multiple higher-level table entries that
+	 * point to the same hugepte.  Just use the first one since they're all
 	 * identical.  So for that case, idx=0.
 	 */
 	unsigned long idx = 0;
 
 	pte_t *dir = hugepd_page(*hpdp);
-#ifdef CONFIG_PPC64
+#ifndef CONFIG_PPC_FSL_BOOK3E
 	idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
 #endif
 
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index b4a4884..9a34606 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -33,17 +33,17 @@ unsigned int HPAGE_SHIFT;
  * implementations may have more than one gpage size due to limitations
  * of the memory allocators, so we need multiple arrays
  */
-#ifdef CONFIG_PPC64
-#define MAX_NUMBER_GPAGES	1024
-static u64 gpage_freearray[MAX_NUMBER_GPAGES];
-static unsigned nr_gpages;
-#else
+#ifdef CONFIG_PPC_FSL_BOOK3E
 #define MAX_NUMBER_GPAGES	128
 struct psize_gpages {
 	u64 gpage_list[MAX_NUMBER_GPAGES];
 	unsigned int nr_gpages;
 };
 static struct psize_gpages gpage_freearray[MMU_PAGE_COUNT];
+#else
+#define MAX_NUMBER_GPAGES	1024
+static u64 gpage_freearray[MAX_NUMBER_GPAGES];
+static unsigned nr_gpages;
 #endif
 
 static inline int shift_to_mmu_psize(unsigned int shift)
@@ -114,12 +114,12 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
 	struct kmem_cache *cachep;
 	pte_t *new;
 
-#ifdef CONFIG_PPC64
-	cachep = PGT_CACHE(pdshift - pshift);
-#else
+#ifdef CONFIG_PPC_FSL_BOOK3E
 	int i;
 	int num_hugepd = 1 << (pshift - pdshift);
 	cachep = hugepte_cache;
+#else
+	cachep = PGT_CACHE(pdshift - pshift);
 #endif
 
 	new = kmem_cache_zalloc(cachep, GFP_KERNEL|__GFP_REPEAT);
@@ -131,12 +131,7 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
 		return -ENOMEM;
 
 	spin_lock(&mm->page_table_lock);
-#ifdef CONFIG_PPC64
-	if (!hugepd_none(*hpdp))
-		kmem_cache_free(cachep, new);
-	else
-		hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
-#else
+#ifdef CONFIG_PPC_FSL_BOOK3E
 	/*
 	 * We have multiple higher-level entries that point to the same
 	 * actual pte location.  Fill in each as we go and backtrack on error.
@@ -215,7 +210,7 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz
 	return hugepte_offset(hpdp, addr, pdshift);
 }
 
-#ifdef CONFIG_PPC32
+#ifdef CONFIG_PPC_FSL_BOOK3E
 /* Build list of addresses of gigantic pages.  This function is used in early
  * boot before the buddy or bootmem allocator is setup.
  */
@@ -335,7 +330,7 @@ void __init reserve_hugetlb_gpages(void)
 	}
 }
 
-#else /* PPC64 */
+#else /* !PPC_FSL_BOOK3E */
 
 /* Build list of addresses of gigantic pages.  This function is used in early
  * boot before the buddy or bootmem allocator is setup.
@@ -373,7 +368,7 @@ int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
 	return 0;
 }
 
-#ifdef CONFIG_PPC32
+#ifdef CONFIG_PPC_FSL_BOOK3E
 #define HUGEPD_FREELIST_SIZE \
 	((PAGE_SIZE - sizeof(struct hugepd_freelist)) / sizeof(pte_t))
 
@@ -433,11 +428,11 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
 	unsigned long pdmask = ~((1UL << pdshift) - 1);
 	unsigned int num_hugepd = 1;
 
-#ifdef CONFIG_PPC64
-	unsigned int shift = hugepd_shift(*hpdp);
-#else
-	/* Note: On 32-bit the hpdp may be the first of several */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+	/* Note: On fsl the hpdp may be the first of several */
 	num_hugepd = (1 << (hugepd_shift(*hpdp) - pdshift));
+#else
+	unsigned int shift = hugepd_shift(*hpdp);
 #endif
 
 	start &= pdmask;
@@ -455,10 +450,11 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
 		hpdp->pd = 0;
 
 	tlb->need_flush = 1;
-#ifdef CONFIG_PPC64
-	pgtable_free_tlb(tlb, hugepte, pdshift - shift);
-#else
+
+#ifdef CONFIG_PPC_FSL_BOOK3E
 	hugepd_free(tlb, hugepte);
+#else
+	pgtable_free_tlb(tlb, hugepte, pdshift - shift);
 #endif
 }
 
@@ -590,12 +586,12 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb,
 				continue;
 			hugetlb_free_pud_range(tlb, pgd, addr, next, floor, ceiling);
 		} else {
-#ifdef CONFIG_PPC32
+#ifdef CONFIG_PPC_FSL_BOOK3E
 			/*
 			 * Increment next by the size of the huge mapping since
-			 * on 32-bit there may be more than one entry at the pgd
-			 * level for a single hugepage, but all of them point to
-			 * the same kmem cache that holds the hugepte.
+			 * there may be more than one entry at the pgd level
+			 * for a single hugepage, but all of them point to the
+			 * same kmem cache that holds the hugepte.
 			 */
 			next = addr + (1 << hugepd_shift(*(hugepd_t *)pgd));
 #endif
@@ -806,7 +802,7 @@ static int __init hugepage_setup_sz(char *str)
 }
 __setup("hugepagesz=", hugepage_setup_sz);
 
-#ifdef CONFIG_FSL_BOOKE
+#ifdef CONFIG_PPC_FSL_BOOK3E
 struct kmem_cache *hugepte_cache;
 static int __init hugetlbpage_init(void)
 {
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index afc95c7..c02901f 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -51,7 +51,7 @@
  * indirect page table entries.
  */
 #ifdef CONFIG_PPC_BOOK3E_MMU
-#ifdef CONFIG_FSL_BOOKE
+#ifdef CONFIG_PPC_FSL_BOOK3E
 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
 	[MMU_PAGE_4K] = {
 		.shift	= 12,
-- 
1.5.6.5

[PATCH 06/13] powerpc: Whitespace/comment changes to tlb_low_64e.S

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

I happened to comment this code while I was digging through it;
we might as well commit that.  I also made some whitespace
changes - the existing code had a lot of unnecessary newlines
that I found annoying when I was working on my tiny laptop.

No functional changes.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/mm/tlb_low_64e.S |   28 +++++++++++-----------------
 1 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index dc4a5f3..71d5d9a 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -94,11 +94,11 @@
 
 	srdi	r15,r16,60		/* get region */
 	rldicl.	r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
-	bne-	dtlb_miss_fault_bolted
+	bne-	dtlb_miss_fault_bolted	/* Bail if fault addr is invalid */
 
 	rlwinm	r10,r11,32-19,27,27
 	rlwimi	r10,r11,32-16,19,19
-	cmpwi	r15,0
+	cmpwi	r15,0			/* user vs kernel check */
 	ori	r10,r10,_PAGE_PRESENT
 	oris	r11,r10,_PAGE_ACCESSED@h
 
@@ -120,44 +120,38 @@ tlb_miss_common_bolted:
 	rldicl	r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
 	cmpldi	cr0,r14,0
 	clrrdi	r15,r15,3
-	beq	tlb_miss_fault_bolted
+	beq	tlb_miss_fault_bolted	/* No PGDIR, bail */
 
 BEGIN_MMU_FTR_SECTION
 	/* Set the TLB reservation and search for existing entry. Then load
 	 * the entry.
 	 */
 	PPC_TLBSRX_DOT(0,r16)
-	ldx	r14,r14,r15
-	beq	normal_tlb_miss_done
+	ldx	r14,r14,r15		/* grab pgd entry */
+	beq	normal_tlb_miss_done	/* tlb exists already, bail */
 MMU_FTR_SECTION_ELSE
-	ldx	r14,r14,r15
+	ldx	r14,r14,r15		/* grab pgd entry */
 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
 
 #ifndef CONFIG_PPC_64K_PAGES
 	rldicl	r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
 	clrrdi	r15,r15,3
-
-	cmpldi	cr0,r14,0
-	beq	tlb_miss_fault_bolted
-
-	ldx	r14,r14,r15
+	cmlpdi	cr0,r14,0
+	beq	tlb_miss_fault_bolted	/* Bad pgd entry */
+	ldx	r14,r14,r15		/* grab pud entry */
 #endif /* CONFIG_PPC_64K_PAGES */
 
 	rldicl	r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
 	clrrdi	r15,r15,3
-
 	cmpldi	cr0,r14,0
 	beq	tlb_miss_fault_bolted
-
-	ldx	r14,r14,r15
+	ldx	r14,r14,r15		/* Grab pmd entry */
 
 	rldicl	r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
 	clrrdi	r15,r15,3
-
 	cmpldi	cr0,r14,0
 	beq	tlb_miss_fault_bolted
-
-	ldx	r14,r14,r15
+	ldx	r14,r14,r15		/* Grab PTE */
 
 	/* Check if required permissions are met */
 	andc.	r15,r11,r14
-- 
1.5.6.5

[PATCH 07/13] powerpc: Add hugepage support to 64-bit tablewalk code for FSL_BOOK3E

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

Before hugetlb, at each level of the table, we test for
!0 to determine if we have a valid table entry.  With hugetlb, this
compare becomes:
        < 0 is a normal entry
        0 is an invalid entry
        > 0 is huge

This works because the hugepage code pulls the top bit off the entry
(which for non-huge entries always has the top bit set) as an
indicator that we have a hugepage.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/mm/tlb_low_64e.S |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index 71d5d9a..ff672bd 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -136,22 +136,22 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
 #ifndef CONFIG_PPC_64K_PAGES
 	rldicl	r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
 	clrrdi	r15,r15,3
-	cmlpdi	cr0,r14,0
-	beq	tlb_miss_fault_bolted	/* Bad pgd entry */
+	cmpdi	cr0,r14,0
+	bge	tlb_miss_fault_bolted	/* Bad pgd entry or hugepage; bail */
 	ldx	r14,r14,r15		/* grab pud entry */
 #endif /* CONFIG_PPC_64K_PAGES */
 
 	rldicl	r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
 	clrrdi	r15,r15,3
-	cmpldi	cr0,r14,0
-	beq	tlb_miss_fault_bolted
+	cmpdi	cr0,r14,0
+	bge	tlb_miss_fault_bolted
 	ldx	r14,r14,r15		/* Grab pmd entry */
 
 	rldicl	r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
 	clrrdi	r15,r15,3
-	cmpldi	cr0,r14,0
-	beq	tlb_miss_fault_bolted
-	ldx	r14,r14,r15		/* Grab PTE */
+	cmpdi	cr0,r14,0
+	bge	tlb_miss_fault_bolted
+	ldx	r14,r14,r15		/* Grab PTE, normal (!huge) page */
 
 	/* Check if required permissions are met */
 	andc.	r15,r11,r14
-- 
1.5.6.5

[PATCH 08/13] powerpc: Add gpages reservation code for 64-bit FSL BOOKE

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

For 64-bit FSL_BOOKE implementations, gigantic pages need to be
reserved at boot time by the memblock code based on the command line.
This adds the call that handles the reservation, and fixes some code
comments.

It also removes the previous pr_err when reserve_hugetlb_gpages
is called on a system without hugetlb enabled - the way the code is
structured, the call is unconditional and the resulting error message
spurious and confusing.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/include/asm/hugetlb.h |   19 ++++++++++++++-----
 arch/powerpc/kernel/setup_64.c     |   10 ++++++++++
 arch/powerpc/mm/hugetlbpage.c      |    8 ++++----
 3 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 273acfa..555044c 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -5,7 +5,6 @@
 #include <asm/page.h>
 
 extern struct kmem_cache *hugepte_cache;
-extern void __init reserve_hugetlb_gpages(void);
 
 static inline pte_t *hugepd_page(hugepd_t hpd)
 {
@@ -153,14 +152,24 @@ static inline void arch_release_hugepage(struct page *page)
 }
 
 #else /* ! CONFIG_HUGETLB_PAGE */
-static inline void reserve_hugetlb_gpages(void)
-{
-	pr_err("Cannot reserve gpages without hugetlb enabled\n");
-}
 static inline void flush_hugetlb_page(struct vm_area_struct *vma,
 				      unsigned long vmaddr)
 {
 }
+#endif /* CONFIG_HUGETLB_PAGE */
+
+
+/*
+ * FSL Book3E platforms require special gpage handling - the gpages
+ * are reserved early in the boot process by memblock instead of via
+ * the .dts as on IBM platforms.
+ */
+#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
+extern void __init reserve_hugetlb_gpages(void);
+#else
+static inline void reserve_hugetlb_gpages(void)
+{
+}
 #endif
 
 #endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index d4168c9..2e334d4 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -35,6 +35,8 @@
 #include <linux/pci.h>
 #include <linux/lockdep.h>
 #include <linux/memblock.h>
+#include <linux/hugetlb.h>
+
 #include <asm/io.h>
 #include <asm/kdump.h>
 #include <asm/prom.h>
@@ -64,6 +66,7 @@
 #include <asm/mmu_context.h>
 #include <asm/code-patching.h>
 #include <asm/kvm_ppc.h>
+#include <asm/hugetlb.h>
 
 #include "setup.h"
 
@@ -217,6 +220,13 @@ void __init early_setup(unsigned long dt_ptr)
 	/* Initialize the hash table or TLB handling */
 	early_init_mmu();
 
+	/*
+	 * Reserve any gigantic pages requested on the command line.
+	 * memblock needs to have been initialized by the time this is
+	 * called since this will reserve memory.
+	 */
+	reserve_hugetlb_gpages();
+
 	DBG(" <- early_setup()\n");
 }
 
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 9a34606..51855a0 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -28,10 +28,10 @@ unsigned int HPAGE_SHIFT;
 
 /*
  * Tracks gpages after the device tree is scanned and before the
- * huge_boot_pages list is ready.  On 64-bit implementations, this is
- * just used to track 16G pages and so is a single array.  32-bit
- * implementations may have more than one gpage size due to limitations
- * of the memory allocators, so we need multiple arrays
+ * huge_boot_pages list is ready.  On non-Freescale implementations, this is
+ * just used to track 16G pages and so is a single array.  FSL-based
+ * implementations may have more than one gpage size, so we need multiple
+ * arrays
  */
 #ifdef CONFIG_PPC_FSL_BOOK3E
 #define MAX_NUMBER_GPAGES	128
-- 
1.5.6.5

[PATCH 09/13] powerpc: Kconfig updates for FSL BookE HUGETLB 64-bit

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

Allow hugetlb to be enabled on 64b FSL_BOOK3E.  No platforms enable
it by default yet.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/platforms/Kconfig.cputype |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index a85990c..7e47fd4 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -174,7 +174,6 @@ config BOOKE
 config FSL_BOOKE
 	bool
 	depends on (E200 || E500) && PPC32
-	select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT
 	default y
 
 # this is for common code between PPC32 & PPC64 FSL BOOKE
@@ -182,6 +181,7 @@ config PPC_FSL_BOOK3E
 	bool
 	select FSL_EMB_PERFMON
 	select PPC_SMP_MUXED_IPI
+	select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64
 	default y if FSL_BOOKE
 
 config PTE_64BIT
@@ -298,7 +298,7 @@ config PPC_BOOK3E_MMU
 
 config PPC_MM_SLICES
 	bool
-	default y if (PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES)
+	default y if (!PPC_FSL_BOOK3E && PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES)
 	default n
 
 config VIRT_CPU_ACCOUNTING
-- 
1.5.6.5

[PATCH 10/13] powerpc: Update mpc85xx/corenet 32-bit defconfigs

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

Results from updates via make savedefconfig.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/configs/corenet32_smp_defconfig |    8 --------
 arch/powerpc/configs/mpc85xx_defconfig       |    5 +----
 arch/powerpc/configs/mpc85xx_smp_defconfig   |    6 +-----
 3 files changed, 2 insertions(+), 17 deletions(-)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 4311d02..ab4db40 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -12,9 +12,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
@@ -69,7 +67,6 @@ CONFIG_IPV6=y
 CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -107,7 +104,6 @@ CONFIG_FSL_PQ_MDIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_LEGACY_PTYS is not set
-CONFIG_PPC_EPAPR_HV_BYTECHAN=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_EXTENDED=y
@@ -136,8 +132,6 @@ CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF=y
-CONFIG_MMC_SDHCI_OF_ESDHC=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_MPC85XX=y
@@ -146,7 +140,6 @@ CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_UIO=y
 CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
 CONFIG_VIRT_DRIVERS=y
 CONFIG_FSL_HV_MANAGER=y
 CONFIG_EXT2_FS=y
@@ -173,7 +166,6 @@ CONFIG_MAC_PARTITION=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=m
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 2500912..a1e5a17 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -10,10 +10,8 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@@ -41,7 +39,6 @@ CONFIG_TQM8560=y
 CONFIG_SBC8548=y
 CONFIG_QUICC_ENGINE=y
 CONFIG_QE_GPIO=y
-CONFIG_GPIO_MPC8XXX=y
 CONFIG_HIGHMEM=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -123,6 +120,7 @@ CONFIG_NVRAM=y
 CONFIG_I2C=y
 CONFIG_I2C_CPM=m
 CONFIG_I2C_MPC=y
+CONFIG_GPIO_MPC8XXX=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
@@ -206,7 +204,6 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
 CONFIG_CRC_T10DIF=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
 CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index a4ba13b..dd1e413 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -12,10 +12,8 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@@ -42,7 +40,6 @@ CONFIG_TQM8560=y
 CONFIG_SBC8548=y
 CONFIG_QUICC_ENGINE=y
 CONFIG_QE_GPIO=y
-CONFIG_GPIO_MPC8XXX=y
 CONFIG_HIGHMEM=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -124,6 +121,7 @@ CONFIG_NVRAM=y
 CONFIG_I2C=y
 CONFIG_I2C_CPM=m
 CONFIG_I2C_MPC=y
+CONFIG_GPIO_MPC8XXX=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
@@ -207,10 +205,8 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
 CONFIG_CRC_T10DIF=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_VIRQ_DEBUG=y
 CONFIG_CRYPTO_PCBC=m
-- 
1.5.6.5

[PATCH 11/13] powerpc: Enable Hugetlb by default for 32-bit 85xx/corenet

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/configs/corenet32_smp_defconfig |    1 +
 arch/powerpc/configs/mpc85xx_defconfig       |    1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig   |    1 +
 3 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index ab4db40..1c328da 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -154,6 +154,7 @@ CONFIG_VFAT_FS=y
 CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index a1e5a17..542eaa1 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -182,6 +182,7 @@ CONFIG_VFAT_FS=y
 CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
 CONFIG_ADFS_FS=m
 CONFIG_AFFS_FS=m
 CONFIG_HFS_FS=m
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index dd1e413..c0a9574 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -183,6 +183,7 @@ CONFIG_VFAT_FS=y
 CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
 CONFIG_ADFS_FS=m
 CONFIG_AFFS_FS=m
 CONFIG_HFS_FS=m
-- 
1.5.6.5

[PATCH 12/13] powerpc: Update corenet64_smp_defconfig

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

Updates from make savedefconfig.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/configs/corenet64_smp_defconfig |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index c92c204..782822c 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -11,10 +11,8 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@@ -25,7 +23,6 @@ CONFIG_P5020_DS=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BINFMT_MISC=m
-# CONFIG_PCI is not set
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -93,10 +90,8 @@ CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_FRAME_WARN=1024
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_VIRQ_DEBUG=y
 CONFIG_CRYPTO_PCBC=m
-- 
1.5.6.5

[PATCH 13/13] powerpc: Enable hugetlb by default for corenet64 platforms

[Becky Bruce]

From: Becky Bruce <beckyb@kernel.crashing.org>

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
---
 arch/powerpc/configs/corenet64_smp_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 782822c..53741f4 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -81,6 +81,7 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
-- 
1.5.6.5

Re: [PATCH 12/13] powerpc: Update corenet64_smp_defconfig

[Kumar Gala]

On Oct 10, 2011, at 3:50 PM, Becky Bruce wrote:

> From: Becky Bruce <beckyb@kernel.crashing.org>
> 
> Updates from make savedefconfig.
> 
> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
> ---
> arch/powerpc/configs/corenet64_smp_defconfig |    5 -----
> 1 files changed, 0 insertions(+), 5 deletions(-)

applied

- k

Re: [PATCH 10/13] powerpc: Update mpc85xx/corenet 32-bit defconfigs

[Kumar Gala]

On Oct 10, 2011, at 3:50 PM, Becky Bruce wrote:

> From: Becky Bruce <beckyb@kernel.crashing.org>
> 
> Results from updates via make savedefconfig.
> 
> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
> ---
> arch/powerpc/configs/corenet32_smp_defconfig |    8 --------
> arch/powerpc/configs/mpc85xx_defconfig       |    5 +----
> arch/powerpc/configs/mpc85xx_smp_defconfig   |    6 +-----
> 3 files changed, 2 insertions(+), 17 deletions(-)

applied

- k

Re: [PATCH 10/13] powerpc: Update mpc85xx/corenet 32-bit defconfigs

[Tabi Timur-B04825]

On Mon, Oct 10, 2011 at 3:50 PM, Becky Bruce <beckyb@kernel.crashing.org> w=
rote:
> From: Becky Bruce <beckyb@kernel.crashing.org>
>
> Results from updates via make savedefconfig.
>
> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
> ---

...

> -CONFIG_PPC_EPAPR_HV_BYTECHAN=3Dy

I guess no one noticed that this patch removes byte channel support,
thereby preventing this kernel from booting under the hypervisor?

--=20
Timur Tabi
Linux kernel developer at Freescale=

Re: [PATCH 04/13] powerpc: Update hugetlb huge_pte_alloc and tablewalk code for FSL BOOKE

[Benjamin Herrenschmidt]

On Mon, 2011-10-10 at 15:50 -0500, Becky Bruce wrote:
> From: Becky Bruce <beckyb@kernel.crashing.org>
> 
> This updates the hugetlb page table code to handle 64-bit FSL_BOOKE.
> The previous 32-bit work counted on the inner levels of the page table
> collapsing.

Seriously, my brain hurts !!!

So I've tried to understand that code and so far, what I came up with is
this, please reply and let me know if I'm full of crack or what ...

 - David's code has entire levels "branching off" into hugepd's which
are hugetlb specific page dirs. That requires address space constrainst.

 - The hack you do with HUGEPD_PGD_SHIFT defined to PGDIR_SHIFT and
HUGEPD_PUD_SHIFT to PUD_SHIFT consists of collasping that back into the
normal levels.

 - I really don't understand what you are doing in __hugepte_alloc(). It
seems to me that you are trying to make things still point to some kind
of separate hugepd dir with the hugeptes in it and have the page tables
point to that but I don't quite get it.

 - Couldn't we just instead ditch the whole hugepd concept alltogether
and simply have the huge ptes in the page table at the right level,
using possibly multiple consecutive of them for a single page when
needed ?

Example: 4K base page size. PMD maps 2M. a 16M page could be
representing by having 8 consecutive hugeptes pointing to the same huge
page in the PMD directory.

I believe we always "know" when accessing a PTE whether it's going to be
huge or not and if it's huge, the page size. IE. All the functions we
care about either get the vma (which gets you everything you need) or
the size (huge_pte_alloc).

This should be much simpler than what we have today.

That way, we have a completely generic accross-the-board way to store
huge pte's in our page tables, which is totally disconnected from the
slices. The later remains a purely server-only thing which only affects
the SLB code and get_unmapped_area().

That means that we'll have to find another option for PowerEN giant
indirects but that's a non issue at the moment. I think we can keep the
complexity local to the PowerEN code by doing shadows there if we need
to.

What do you think ?

Ben.

Re: [PATCH 04/13] powerpc: Update hugetlb huge_pte_alloc and tablewalk code for FSL BOOKE

[Becky Bruce]

On Nov 28, 2011, at 11:25 PM, Benjamin Herrenschmidt wrote:

> On Mon, 2011-10-10 at 15:50 -0500, Becky Bruce wrote:
>> From: Becky Bruce <beckyb@kernel.crashing.org>
>>=20
>> This updates the hugetlb page table code to handle 64-bit FSL_BOOKE.
>> The previous 32-bit work counted on the inner levels of the page =
table
>> collapsing.
>=20
> Seriously, my brain hurts !!!

Now you know how I felt when I got the original code from David :)

>=20
> So I've tried to understand that code and so far, what I came up with =
is
> this, please reply and let me know if I'm full of crack or what ...
>=20
> - David's code has entire levels "branching off" into hugepd's which
> are hugetlb specific page dirs. That requires address space =
constrainst.

Yes.

>=20
> - The hack you do with HUGEPD_PGD_SHIFT defined to PGDIR_SHIFT and
> HUGEPD_PUD_SHIFT to PUD_SHIFT consists of collasping that back into =
the
> normal levels.

That exists so Jimi's code for A2 and mine can coexist peacefully =
without ifdeffing huge blocks because we peel off the page table at =
different points for a hugepd.  In my case, if I have a 4M page, that is =
handled by having 2 entries at the 2M layer, each of which is a pointer =
to the same pte stored in a kmem_cache created for that purpose.  In the =
server/A2 case, they peel off at the layer above 4M and have a sub-table =
kmem_cache that has a bunch of same-size huge page ptes (this is all =
because of the slice constraint).

>=20
> - I really don't understand what you are doing in __hugepte_alloc(). =
It
> seems to me that you are trying to make things still point to some =
kind
> of separate hugepd dir with the hugeptes in it and have the page =
tables
> point to that but I don't quite get it.

In your example below, the alloc code is:
1) allocating a small kmem_cache for the pte

2) filling in 8 entries at the 2M level with the pointers to that pte, =
with the upper bit munged to indicate huge and bits in the lower region =
that store the huge page size because it can't be encoded in the book3e =
pte format

>=20
> - Couldn't we just instead ditch the whole hugepd concept alltogether
> and simply have the huge ptes in the page table at the right level,
> using possibly multiple consecutive of them for a single page when
> needed ?
>=20
> Example: 4K base page size. PMD maps 2M. a 16M page could be
> representing by having 8 consecutive hugeptes pointing to the same =
huge
> page in the PMD directory.

We currently have 8 consecutive PMD entries that are pointers to the =
same kmem_cache that holds the actual PTE.  I did this for a few =
reasons:

1) I was trying to stay as close to what David had done as possible

2) symmetry - in every other case entries at higher levels of the normal =
page table are pointers to something, and it's easy to identify that =
something is a pointer to hugepte using David's upper-bit-flipping =
trick.  If we have an actual entry mixed in with the pointers it might =
be hard to tell that's it's an actual PTE and not a pointer without =
getting information from somewhere else (i.e. the vma)

3) I was trying to avoid having multiple copies of the actual pte - this =
way it's easy to do stuff like change the perms on the PTE, since I only =
have to modify one copy

4) I needed the information laid out for quick TLB miss fault-handling =
of hugepte tlb misses (see below).

>=20
> I believe we always "know" when accessing a PTE whether it's going to =
be
> huge or not and if it's huge, the page size. IE. All the functions we
> care about either get the vma (which gets you everything you need) or
> the size (huge_pte_alloc).

An exception is the 32-bit fault hander asm code.  It does a walk of the =
page table to reload the tlb.  We need to be able to easily identify =
that we're walking into a hugepage area so we know to load the tlbcam.  =
Having the pointer there with the munged upper bit that David devised is =
very convenient for that.  Also, the Book3e page table format does not =
allow us to represent page sizes > 32m.  So that's encoded in the hugepd =
instead (and not in the pte).

I'm not sure how to get around this without slowing things down.  I =
originally had a slower handler and it turned out to impact performance =
of several important workloads and my perf guys griped at me. I was =
actually eventually planning to rewrite the 64b fsl book3e handler to =
deal with this in asm as well.   Large workloads on our systems do a lot =
of tlbcam entry replacement due to 1) the small size of the tlbcam and =
2) the lack of any hardware replacement policy on that array.

There are other places where we'd have to modify the code to have the =
vma available (not that it's hard to do, but it's not floating around =
everywhere).  And there may be other places where this is an issue - I'd =
have to go dig around a bit to answer that.

For the record, I hate the idea of not being able to walk the page table =
without going elsewhere for information.  IMHO I should be able to tell =
everything I need to load a TLB entry from there without digging up a =
vma.

>=20
> This should be much simpler than what we have today.
>=20
> That way, we have a completely generic accross-the-board way to store
> huge pte's in our page tables, which is totally disconnected from the
> slices. The later remains a purely server-only thing which only =
affects
> the SLB code and get_unmapped_area().

David and Jimi will have to comment about whether they can flatten out =
their stuff to just store PTEs.  A lot of my code exists because I was =
attempting to be as close to the IBM implementation as possible.

>=20
> That means that we'll have to find another option for PowerEN giant
> indirects but that's a non issue at the moment. I think we can keep =
the
> complexity local to the PowerEN code by doing shadows there if we need
> to.
>=20
> What do you think ?

I'm happy if we can come up with another solution that still allows me =
to do my miss fault handling efficiently in asm.... What we do on FSL =
Booke with storing multiple pointers to a single pte is actually a =
fairly clean solution given the constraints.  It's only in the context =
of having a different implementation coexisting with it that makes =
things start getting complicated.  If you have some suggestions on =
another way to deal with this, I'm all ears.

Cheers,
B

Re: [PATCH 04/13] powerpc: Update hugetlb huge_pte_alloc and tablewalk code for FSL BOOKE

[David Gibson]

On Tue, Nov 29, 2011 at 10:36:42AM -0600, Becky Bruce wrote:
> 
> On Nov 28, 2011, at 11:25 PM, Benjamin Herrenschmidt wrote:
> 
> > On Mon, 2011-10-10 at 15:50 -0500, Becky Bruce wrote:
> >> From: Becky Bruce <beckyb@kernel.crashing.org>
> >> 
> >> This updates the hugetlb page table code to handle 64-bit FSL_BOOKE.
> >> The previous 32-bit work counted on the inner levels of the page table
> >> collapsing.
> > 
> > Seriously, my brain hurts !!!
> 
> Now you know how I felt when I got the original code from David :)

Heh, I can't blame you.  Between the constraints of the hardware and
fitting in with x86, that thing's accreted into a horrible pile.

> > So I've tried to understand that code and so far, what I came up with is
> > this, please reply and let me know if I'm full of crack or what ...
> > 
> > - David's code has entire levels "branching off" into hugepd's which
> > are hugetlb specific page dirs. That requires address space constrainst.
> 
> Yes.
> 
> > - The hack you do with HUGEPD_PGD_SHIFT defined to PGDIR_SHIFT and
> > HUGEPD_PUD_SHIFT to PUD_SHIFT consists of collasping that back into the
> > normal levels.
> 
> That exists so Jimi's code for A2 and mine can coexist peacefully
> without ifdeffing huge blocks because we peel off the page table at
> different points for a hugepd.  In my case, if I have a 4M page,
> that is handled by having 2 entries at the 2M layer, each of which
> is a pointer to the same pte stored in a kmem_cache created for that
> purpose.  In the server/A2 case, they peel off at the layer above 4M
> and have a sub-table kmem_cache that has a bunch of same-size huge
> page ptes (this is all because of the slice constraint).
> 
> > - I really don't understand what you are doing in __hugepte_alloc(). It
> > seems to me that you are trying to make things still point to some kind
> > of separate hugepd dir with the hugeptes in it and have the page tables
> > point to that but I don't quite get it.
> 
> In your example below, the alloc code is:
> 1) allocating a small kmem_cache for the pte
> 
> 2) filling in 8 entries at the 2M level with the pointers to that pte, with the upper bit munged to indicate huge and bits in the lower region that store the huge page size because it can't be encoded in the book3e pte format
> 
> > - Couldn't we just instead ditch the whole hugepd concept alltogether
> > and simply have the huge ptes in the page table at the right level,
> > using possibly multiple consecutive of them for a single page when
> > needed ?
> > 
> > Example: 4K base page size. PMD maps 2M. a 16M page could be
> > representing by having 8 consecutive hugeptes pointing to the same huge
> > page in the PMD directory.
> 
> We currently have 8 consecutive PMD entries that are pointers to the
> same kmem_cache that holds the actual PTE.  I did this for a few
> reasons:
> 
> 1) I was trying to stay as close to what David had done as possible
> 
> 2) symmetry - in every other case entries at higher levels of the
> normal page table are pointers to something, and it's easy to
> identify that something is a pointer to hugepte using David's
> upper-bit-flipping trick.  If we have an actual entry mixed in with
> the pointers it might be hard to tell that's it's an actual PTE and
> not a pointer without getting information from somewhere else
> (i.e. the vma)
> 
> 3) I was trying to avoid having multiple copies of the actual pte -
> this way it's easy to do stuff like change the perms on the PTE,
> since I only have to modify one copy
> 
> 4) I needed the information laid out for quick TLB miss
> fault-handling of hugepte tlb misses (see below).
> 
> > I believe we always "know" when accessing a PTE whether it's going to be
> > huge or not and if it's huge, the page size. IE. All the functions we
> > care about either get the vma (which gets you everything you need) or
> > the size (huge_pte_alloc).
> 
> An exception is the 32-bit fault hander asm code.  It does a walk of
> the page table to reload the tlb.  We need to be able to easily
> identify that we're walking into a hugepage area so we know to load
> the tlbcam.  Having the pointer there with the munged upper bit that
> David devised is very convenient for that.  Also, the Book3e page
> table format does not allow us to represent page sizes > 32m.  So
> that's encoded in the hugepd instead (and not in the pte).
> 
> I'm not sure how to get around this without slowing things down.  I
> originally had a slower handler and it turned out to impact
> performance of several important workloads and my perf guys griped
> at me. I was actually eventually planning to rewrite the 64b fsl
> book3e handler to deal with this in asm as well.  Large workloads on
> our systems do a lot of tlbcam entry replacement due to 1) the small
> size of the tlbcam and 2) the lack of any hardware replacement
> policy on that array.
> 
> There are other places where we'd have to modify the code to have
> the vma available (not that it's hard to do, but it's not floating
> around everywhere).  And there may be other places where this is an
> issue - I'd have to go dig around a bit to answer that.
> 
> For the record, I hate the idea of not being able to walk the page
> table without going elsewhere for information.  IMHO I should be
> able to tell everything I need to load a TLB entry from there
> without digging up a vma.

I agree, all things being equal, but there might be tradeoffs that
make it the least bad option.

> > This should be much simpler than what we have today.
> > 
> > That way, we have a completely generic accross-the-board way to store
> > huge pte's in our page tables, which is totally disconnected from the
> > slices. The later remains a purely server-only thing which only affects
> > the SLB code and get_unmapped_area().
> 
> David and Jimi will have to comment about whether they can flatten
> out their stuff to just store PTEs.  A lot of my code exists because
> I was attempting to be as close to the IBM implementation as
> possible.

I was talking with Ben about this yesterday, and I think it can
probably be done.

> > That means that we'll have to find another option for PowerEN giant
> > indirects but that's a non issue at the moment. I think we can keep the
> > complexity local to the PowerEN code by doing shadows there if we need
> > to.
> > 
> > What do you think ?
> 
> I'm happy if we can come up with another solution that still allows
> me to do my miss fault handling efficiently in asm.... What we do on
> FSL Booke with storing multiple pointers to a single pte is actually
> a fairly clean solution given the constraints.  It's only in the
> context of having a different implementation coexisting with it that
> makes things start getting complicated.  If you have some
> suggestions on another way to deal with this, I'm all ears.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 03/13] powerpc: Fix booke hugetlb preload code for PPC_MM_SLICES and 64-bit

[Benjamin Herrenschmidt]

On Mon, 2011-10-10 at 15:50 -0500, Becky Bruce wrote:

 .../...

>  #ifdef CONFIG_PPC_MM_SLICES
> -	psize = mmu_get_tsize(get_slice_psize(mm, ea));
> -	tsize = mmu_get_psize(psize);
> +	psize = get_slice_psize(mm, ea);
> +	tsize = mmu_get_tsize(psize);
>  	shift = mmu_psize_defs[psize].shift;
>  #else
> -	vma = find_vma(mm, ea);
> -	psize = vma_mmu_pagesize(vma);	/* returns actual size in bytes */
> -	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (psize));
> -	shift = 31 - lz;
> -	tsize = 21 - lz;
> +	psize = vma_mmu_pagesize(find_vma(mm, ea));
> +	shift = __ilog2(psize);
> +	tsize = shift - 10;
>  #endif

Now, I know it was already there and you are just moving it around in
this patch but come on ... find_vma() here ? Really ? And with no result
checking nor boundary checking (remember it can return a vma that
doesn't enclose the address etc....). Now I know in this specific case
it -should- be safe but still...

Now, the caller is just doing:
 
	book3e_hugetlb_preload(vma->vm_mm, address, *ptep);

So why not just change the prototype and pass the vma down instead ?

Cheers,
Ben.

Re: [PATCH 03/13] powerpc: Fix booke hugetlb preload code for PPC_MM_SLICES and 64-bit

[Kumar Gala]

On Nov 24, 2011, at 6:43 PM, Benjamin Herrenschmidt wrote:

> On Mon, 2011-10-10 at 15:50 -0500, Becky Bruce wrote:
>=20
> .../...
>=20
>> #ifdef CONFIG_PPC_MM_SLICES
>> -	psize =3D mmu_get_tsize(get_slice_psize(mm, ea));
>> -	tsize =3D mmu_get_psize(psize);
>> +	psize =3D get_slice_psize(mm, ea);
>> +	tsize =3D mmu_get_tsize(psize);
>> 	shift =3D mmu_psize_defs[psize].shift;
>> #else
>> -	vma =3D find_vma(mm, ea);
>> -	psize =3D vma_mmu_pagesize(vma);	/* returns actual size =
in bytes */
>> -	asm (PPC_CNTLZL "%0,%1" : "=3Dr" (lz) : "r" (psize));
>> -	shift =3D 31 - lz;
>> -	tsize =3D 21 - lz;
>> +	psize =3D vma_mmu_pagesize(find_vma(mm, ea));
>> +	shift =3D __ilog2(psize);
>> +	tsize =3D shift - 10;
>> #endif
>=20
> Now, I know it was already there and you are just moving it around in
> this patch but come on ... find_vma() here ? Really ? And with no =
result
> checking nor boundary checking (remember it can return a vma that
> doesn't enclose the address etc....). Now I know in this specific case
> it -should- be safe but still...
>=20
> Now, the caller is just doing:
>=20
> 	book3e_hugetlb_preload(vma->vm_mm, address, *ptep);
>=20
> So why not just change the prototype and pass the vma down instead ?

Can we do this on top of the patchset instead of changing the existing =
patchset?

- k=

Re: [PATCH 03/13] powerpc: Fix booke hugetlb preload code for PPC_MM_SLICES and 64-bit

[Becky Bruce]

On Nov 24, 2011, at 6:43 PM, Benjamin Herrenschmidt wrote:

> On Mon, 2011-10-10 at 15:50 -0500, Becky Bruce wrote:
>=20
> .../...
>=20
>> #ifdef CONFIG_PPC_MM_SLICES
>> -	psize =3D mmu_get_tsize(get_slice_psize(mm, ea));
>> -	tsize =3D mmu_get_psize(psize);
>> +	psize =3D get_slice_psize(mm, ea);
>> +	tsize =3D mmu_get_tsize(psize);
>> 	shift =3D mmu_psize_defs[psize].shift;
>> #else
>> -	vma =3D find_vma(mm, ea);
>> -	psize =3D vma_mmu_pagesize(vma);	/* returns actual size =
in bytes */
>> -	asm (PPC_CNTLZL "%0,%1" : "=3Dr" (lz) : "r" (psize));
>> -	shift =3D 31 - lz;
>> -	tsize =3D 21 - lz;
>> +	psize =3D vma_mmu_pagesize(find_vma(mm, ea));
>> +	shift =3D __ilog2(psize);
>> +	tsize =3D shift - 10;
>> #endif
>=20
> Now, I know it was already there and you are just moving it around in
> this patch but come on ... find_vma() here ? Really ? And with no =
result
> checking nor boundary checking (remember it can return a vma that
> doesn't enclose the address etc....). Now I know in this specific case
> it -should- be safe but still...
>=20
> Now, the caller is just doing:
>=20
> 	book3e_hugetlb_preload(vma->vm_mm, address, *ptep);
>=20
> So why not just change the prototype and pass the vma down instead ?

There's no reason - I just left the prototype the way it was in the =
original code, but it makes sense to change it given the changes to the =
function.  Respin coming.....

-B

Re: [PATCH 03/13] powerpc: Fix booke hugetlb preload code for PPC_MM_SLICES and 64-bit

[Benjamin Herrenschmidt]

> 	return;
>  
>  #ifdef CONFIG_PPC_MM_SLICES
> -	psize = mmu_get_tsize(get_slice_psize(mm, ea));
> -	tsize = mmu_get_psize(psize);
> +	psize = get_slice_psize(mm, ea);
> +	tsize = mmu_get_tsize(psize);
>  	shift = mmu_psize_defs[psize].shift;
>  #else
> -	vma = find_vma(mm, ea);
> -	psize = vma_mmu_pagesize(vma);	/* returns actual size in bytes */
> -	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (psize));
> -	shift = 31 - lz;
> -	tsize = 21 - lz;
> +	psize = vma_mmu_pagesize(find_vma(mm, ea));
> +	shift = __ilog2(psize);
> +	tsize = shift - 10;
>  #endif
>  

BTW. Can you remind me what is the business with slices vs. no slices on
Book3E ?

I'd like to avoid having to build separate kernels for A2 vs. FSL ... 

Cheers,
Ben.

Re: [PATCH 02/13] powerpc: hugetlb: fix huge_ptep_set_access_flags return value

[Benjamin Herrenschmidt]

On Mon, 2011-10-10 at 15:50 -0500, Becky Bruce wrote:

> diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
> index 8600493..70f9885 100644
> --- a/arch/powerpc/include/asm/hugetlb.h
> +++ b/arch/powerpc/include/asm/hugetlb.h
> @@ -124,7 +124,18 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
>  					     unsigned long addr, pte_t *ptep,
>  					     pte_t pte, int dirty)
>  {
> +#if defined(CONFIG_PPC_MMU_NOHASH) && \
> +	!(defined(CONFIG_PPC_FSL_BOOK3E) && defined(CONFIG_PPC32))

The above conditional makes my brain hurt. Can you change that to
instead

#ifdef HUGETLB_NEED_PRELOAD

 ... or something like that, which you then #define in the right
mmu-xxxx.h header ?

Cheers,
Ben.


> +	/*
> +	 * The "return 1" forces a call of update_mmu_cache, which will write a
> +	 * TLB entry.  Without this, platforms that don't do a write of the TLB
> +	 * entry in the TLB miss handler asm will fault ad infinitum.
> +	 */
> +	ptep_set_access_flags(vma, addr, ptep, pte, dirty);
> +	return 1;
> +#else
>  	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
> +#endif
>  }
>  
>  static inline pte_t huge_ptep_get(pte_t *ptep)

Re: [PATCH 02/13] powerpc: hugetlb: fix huge_ptep_set_access_flags return value

[Becky Bruce]

On Nov 28, 2011, at 9:58 PM, Benjamin Herrenschmidt wrote:

> On Mon, 2011-10-10 at 15:50 -0500, Becky Bruce wrote:
>=20
>> diff --git a/arch/powerpc/include/asm/hugetlb.h =
b/arch/powerpc/include/asm/hugetlb.h
>> index 8600493..70f9885 100644
>> --- a/arch/powerpc/include/asm/hugetlb.h
>> +++ b/arch/powerpc/include/asm/hugetlb.h
>> @@ -124,7 +124,18 @@ static inline int =
huge_ptep_set_access_flags(struct vm_area_struct *vma,
>> 					     unsigned long addr, pte_t =
*ptep,
>> 					     pte_t pte, int dirty)
>> {
>> +#if defined(CONFIG_PPC_MMU_NOHASH) && \
>> +	!(defined(CONFIG_PPC_FSL_BOOK3E) && defined(CONFIG_PPC32))
>=20
> The above conditional makes my brain hurt. Can you change that to
> instead
>=20
> #ifdef HUGETLB_NEED_PRELOAD
>=20
> ... or something like that, which you then #define in the right
> mmu-xxxx.h header ?

Sure.

Can I publish this as a followup instead of rebasing?  We're trying to =
stay sync'ed with what's in our BSP and it would be easier for me/Kumar =
to deal with.

Cheers,
B

>=20
> Cheers,
> Ben.
>=20
>=20
>> +	/*
>> +	 * The "return 1" forces a call of update_mmu_cache, which will =
write a
>> +	 * TLB entry.  Without this, platforms that don't do a write of =
the TLB
>> +	 * entry in the TLB miss handler asm will fault ad infinitum.
>> +	 */
>> +	ptep_set_access_flags(vma, addr, ptep, pte, dirty);
>> +	return 1;
>> +#else
>> 	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
>> +#endif
>> }
>>=20
>> static inline pte_t huge_ptep_get(pte_t *ptep)
>=20