PCI architecture enlightenment

PCI architecture enlightenment

[Allen Curtis]

I was wondering if anyone could provide enlightenment on the PCI address
translation architecture. I have been looking at the code and it is not
obvious how all the different pieces fit together. I read
Documentation/pci.txt and it refers to device drivers not host controller
configuration and resource allocation.0

Our board:
Host phys: 0x40000000 - 0x47ffffff	=>
PCI I/O space 0x00000000 - 0x07ffffff

Host phys: 0x48000000 - 0x4fffffff =>
PCI Memory space 0x00000000 - 0x07ffffff

PCI phys: 0x40000000 -  0x47ffffff =>
Host Memory 0x00000000 - 0x07ffffff

Host Memory:
phys: 0x00000000
virt: 0xc0000000
size: 0x08000000

PCI BAR: (only 1 bus)
Memory: 0x00000000
I/O:    0x00000000

======================

When initializing a host controller how do the following interact?

hose->io_start/io_end
host->mem_start/mem_end
host->virt_io_addr

pci_init_resource(IO)
pci_init_resource(MEM)

PCI_ISA_IO...
PCI_ISA_MEM...
PCI_DRAM_OFFSET
_IO_BASE

Somehow the above information is used to create a host->PCI memory map,
PCI->host memory map and PCI->PCI memory map.

TIA


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Re: PCI architecture enlightenment

[Benjamin Herrenschmidt]

>Our board:
>Host phys: 0x40000000 - 0x47ffffff	=>
>PCI I/O space 0x00000000 - 0x07ffffff

You setup:

 hose->io_base_phys to 0x40000000
 hose->io_base_virt to ioremap(0x40000000, size)

Beware _NOT_ to ioremap too much space for IO space. 16Mb
shoud be plenty enough. The kernel is a bit "short" on ioremap
space, mapping too much would cause possible exhaustion of it
and collision between ioremap/vmalloc space and linear memory
mapping.

Then, you setup hose->io_resource.flags to IORESOURCE_IO
and hose->io_resource.start to the bus view start, that is 0.
and hose->io_resource->end to the end of that IO window

Then, also do isa_io_base = hose->io_base_virt for legacy
drivers doing inx/outx to go tap that IO bus.

>Host phys: 0x48000000 - 0x4fffffff =>
>PCI Memory space 0x00000000 - 0x07ffffff

Here, you setup your host->PCI memory mapping. Fill up
hose->mem_resources[0].start/end to be the start/end of the
CPU side memory space view, that is 0x48000000 & 0x4fffffff,
then set hose->pci_mem_offset to be the the offset between
that CPU side view and the PCI side view, that is 0x48000000
and hose->mem_resources[0].flags to IORESOURCE_MEM
Since that region also give access to ISA memory, set
isa_mem_base to 0x48000000 as well.


>PCI phys: 0x40000000 -  0x47ffffff =>
>Host Memory 0x00000000 - 0x07ffffff

Your host memory is visible at PCI 0x40000000, so put that
value in pci_dram_offset.

So the actual setup should look like

 hose->io_base_phys           = 0x40000000;
 hose->io_base_virt           = ioremap(0x40000000, 0x01000000);
 hose->io_resource.start      = 0;
 hose->io_resource.end        = 0x01000000;
 hose->io_resource.flags      = IORESOURCE_IO;
 isa_io_base                  = hose->io_base_virt;

 hose->mem_resources[0].start = 0x48000000;
 hose->mem_resources[0].end   = 0x4fffffff;
 hose->mem_resources[0].flags = IORESOURCE_MEM;
 hose->pci_mem_offset         = 0x48000000;
 isa_mem_base                 = 0x48000000;
 pci_dram_offset              = 0x40000000;


>Host Memory:
>phys: 0x00000000
>virt: 0xc0000000
>size: 0x08000000
>
>PCI BAR: (only 1 bus)
>Memory: 0x00000000
>I/O:    0x00000000

Beware that if your host bridge appears as a PCI device on the BUS and
his BAR may for some reasons be incorrectly considered as a device BAR
while it's actually used to configure the bridge ranges (typically what
happens with a 405gp or a CPC710), then you need to "hide" this BAR, using
a PCI quirk (see the fixups in arch/ppc/kernel/pci.c)

Ben.


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RE: PCI architecture enlightenment

[acurtis]

> So the actual setup should look like
>
>  hose->io_base_phys           = 0x40000000;
>  hose->io_base_virt           = ioremap(0x40000000, 0x01000000);
>  hose->io_resource.start      = 0;
>  hose->io_resource.end        = 0x01000000;
>  hose->io_resource.flags      = IORESOURCE_IO;
>  isa_io_base                  = hose->io_base_virt;
>
>  hose->mem_resources[0].start = 0x48000000;
>  hose->mem_resources[0].end   = 0x4fffffff;
>  hose->mem_resources[0].flags = IORESOURCE_MEM;
>  hose->pci_mem_offset         = 0x48000000;
>  isa_mem_base                 = 0x48000000;
>  pci_dram_offset              = 0x40000000;
>

I think this is the configuration I have but will double check. Thanks for
the explanation. It is so much easier to work on something when you do not
think you are just putting things in variables without any idea why.

> Beware that if your host bridge appears as a PCI device on the BUS and
> his BAR may for some reasons be incorrectly considered as a device BAR
> while it's actually used to configure the bridge ranges (typically what
> happens with a 405gp or a CPC710), then you need to "hide" this BAR, using
> a PCI quirk (see the fixups in arch/ppc/kernel/pci.c)

There are 2 BAR's for the host controller that appear but they do not get
assigned resources since they fall outside of the defined resources ranges.
So, this should matter right? (see PCI/SCSI help message for output)


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RE: PCI architecture enlightenment

[Allen Curtis]

> There are 2 BAR's for the host controller that appear but they do not get
> assigned resources since they fall outside of the defined resources ranges.
> So, this should matter right? (see PCI/SCSI help message for output)

Should read "So, this should NOT matter...."

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