From: "Allen Curtis" <acurtis@onz.com>
To: "Paul Mackerras" <paulus@samba.org>
Cc: <linuxppc-dev@lists.linuxppc.org>
Subject: RE: eieio rule-of-thumb?
Date: Wed, 22 May 2002 19:25:56 -0700 [thread overview]
Message-ID: <NCBBIINEHIPFGJPLBEIFOEHMDHAA.acurtis@onz.com> (raw)
In-Reply-To: <15595.13374.704999.529737@argo.ozlabs.ibm.com>
>Nope. Loads can (and sometimes do) go ahead of stores. Stores can go
>ahead of loads as well in some circumstances, for example if the load
>is non-cacheable and the store hits in the cache. In principle loads
>can get reordered too. Reordering can happen in the processor's
>load/store unit and/or in the PCI host bridge.
>
>I assume you are mostly concerned with loads and stores to
>noncacheable addresses (i.e. I/O devices). Non-cacheable stores don't
>get reordered, and eieio acts as a barrier to make sure that all
>noncacheable accesses before the eieio are done before any of the
>noncacheable accesses after the eieio.
Could you provide an example of when you should insert this instruction into
your code. From you description it is a wonder that "var += 2;" works if I
am accessing dual-port on an 8260.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2002-05-23 2:25 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-05-22 4:43 eieio rule-of-thumb? Allen Curtis
2002-05-22 6:01 ` Paul Mackerras
2002-05-23 2:25 ` Allen Curtis [this message]
2002-05-23 4:26 ` Paul Mackerras
2002-05-23 13:38 ` Allen Curtis
2002-05-23 13:54 ` Dan Brennan
2002-05-23 14:42 ` Allen Curtis
2002-05-23 17:28 ` Dan Malek
2002-05-23 17:45 ` Chris Thomson
2002-05-23 19:02 ` Dan Malek
2002-05-23 22:36 ` Paul Mackerras
2002-05-23 18:44 ` benh
2002-05-23 18:02 ` Dan Malek
2002-05-23 22:58 ` Paul Mackerras
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