RE: "Illegal instruction" traps on smp clients - 2.4.19

["David Bryan" <Dave@ThePTRGroup.com>]

Michael,

Certainly, be glad to...  however, I would make sure you fully understand
the operation of these bits and their applicability to your system.

On the 7400/7410 the MSSCR0 is accessed as SPR 1014.

At reset, the MSSCR0 is initialized to all 0s.

We OR'd 0x8000 with MSSCR0.

Bit 0 (MSB) controls whether the 7400 runs MEI or MESI coherency protocol.
Setting Bit 0 (SHDEN) causes the 7400 to implement "a 4-state MESI protocol
similar to the MPC604e family of processors".  Bit 1 (SHDPEN3) is valid only
in MEI mode, so its value is ignored when SHDEN is set.  In this
configuration, the 7400 will drive/sample the SHD/0/1 pins depending on the
bus mode (MPX or 60x).


Dave

David Bryan                www.ThePTRGroup.com
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-----Original Message-----
From: Michael R. Zucca [mailto:mrz5149@acm.org]
Sent: Thursday, February 27, 2003 1:26 PM
To: David Bryan
Cc: Rudy Klinksiek; linuxppc-dev@lists.linuxppc.org
Subject: Re: "Illegal instruction" traps on smp clients - 2.4.19


David Bryan wrote:
 > These modes are controlled by two bits in
> the Memory subsystem control register (MSSCR0).  At reset, the MSSCR0
> defaults to MEI mode with the SHD signal disabled.  By placing the 7400 in
> MESI mode at boot, we solved the problem.

Would you care to share what MSSCR0 bits these were and what you set
them to? :-)

--
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  Michael Zucca - mrz5149@acm.org
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  "I'm too old to use Emacs." -- Rod MacDonald
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