From: "soar.wu" <soar.wu@utstar.com>
To: "Mark Chambers" <markc@mail.com>, <linuxppc-embedded@ozlabs.org>
Subject: RE: Help!
Date: Wed, 27 Oct 2004 11:47:36 +0800 [thread overview]
Message-ID: <PCEFKKAFFIJFPILJEMCHMEAOCGAA.soar.wu@utstar.com> (raw)
In-Reply-To: <00c201c4bb66$0139ccc0$0301a8c0@chuck2>
[-- Attachment #1: Type: text/plain, Size: 2480 bytes --]
The attached file is the hpi_ul_memcpy_dsp2h() function.
Yes, the 'HPI' - are connected to a T.I. DSP, 6416 type.
About the HPI problem progress.
now we have the following resolve method:
1, If we use a temp variable to store the read out data, then store the data to SDRAM, it is OK, there is no hop.
tmpReadRst = READ_UL_HPI_REG(UL_HPIDA_ADDR);
*p_cur = tmpReadRst;
p_cur++;
2, If we donot modify the source codes, but we use the optimization O3 to compile the source codes, it is OK.
*p_cur = READ_UL_HPI_REG(UL_HPIDA_ADDR);
p_cur++;
3, If we add a sync instruction to the source codes, it is OK.
*p_cur = READ_UL_HPI_REG(UL_HPIDA_ADDR);
__asm__(" eieio; sync");
p_cur++;
4, If we modify the BSP, update the memory operation option,
from :
PHYS_MEM_DESC sysPhysMemDesc [] =
{
...
/*all the other small chip*/
{
(void *) 0x50000000,
(void *) 0x50000000,
0x08000000,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
...
to:
PHYS_MEM_DESC sysPhysMemDesc [] =
{
...
/*all the other small chip*/
{
(void *) 0x50000000,
(void *) 0x50000000,
0x08000000,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
},
...
We added the option VM_STATE_VM_MASK_GUARDED and VM_STATE_GUARDED,
still use the old source codes:
*p_cur = READ_UL_HPI_REG(UL_HPIDA_ADDR);
p_cur++;
Now We find there is no hop. It is OK
5, If we use the memory which is allocated by function cacheDmaMalloc(),
the hop still exist, but the number of hop is little than when we use malloc().
Do you tell me the reason??
Wait for your reply.
Best Regards,
Soar Wu
-----Original Message-----
From: Mark Chambers [mailto:markc@mail.com]
Sent: 2004年10月26日 22:13
To: soar.wu; linuxppc-embedded@ozlabs.org
Subject: Re: Help!
Clear Day>Firstly we will write data to the HPI,
>then read data from the HPI to the SDRAM(this SDRAM is connected with
60x-BUS).
>The last we will read the data from the SDRAM to compare the data which is
write >to HPI.
Can you show the entire source for hpi_ul_memcpy_dsp2h()?
Also, you say 'HPI' - are connected to a T.I. DSP? Which one?
Mark Chambers
[-- Attachment #2: dsp2h.txt --]
[-- Type: text/plain, Size: 4031 bytes --]
void hpi_ul_memcpy_dsp2h(void *dest,U32 src_dsp_memory_addr, U32 count)
{
0x9ee8bc hpi_ul_memcpy_dsp2h: stwu r1, 0xffd0(r1)
0x9ee8c0 +0x004: mfspr r0, LR
0x9ee8c4 +0x008: stw r31, 0x2c(r1)
0x9ee8c8 +0x00c: stw r0, 0x34(r1)
0x9ee8cc +0x010: or r31, r1, r1
0x9ee8d0 +0x014: stw r3, 0x8(r31)
0x9ee8d4 +0x018: stw r4, 0xc(r31)
0x9ee8d8 +0x01c: stw r5, 0x10(r31)
U32 *p_cur = dest;
0x9ee8dc +0x020: lwz r0, 0x8(r31)
0x9ee8e0 +0x024: stw r0, 0x14(r31)
U32 i,len;
U32 scraddr = src_dsp_memory_addr;
0x9ee8e4 +0x028: lwz r0, 0xc(r31)
0x9ee8e8 +0x02c: stw r0, 0x20(r31)
len = DWORD_ALIGN(count);
0x9ee8ec +0x030: lwz r9, 0x10(r31)
0x9ee8f0 +0x034: addi r0, r9, 0x3 (3)
0x9ee8f4 +0x038: rlwinm r9, r0, 0x1e, 2, 31
0x9ee8f8 +0x03c: or r0, r9, r9
0x9ee8fc +0x040: rlwinm r9, r0, 0x2, 0, 29
0x9ee900 +0x044: stw r9, 0x1c(r31)
HPI_UL_LOCK();
0x9ee904 +0x048: lis r9, 0x9f (159)
0x9ee908 +0x04c: addi r11, r9, 0x6d8 (1752)
0x9ee90c +0x050: lwz r3, 0x0(r11)
0x9ee910 +0x054: li r4, 0xffff (-1)
0x9ee914 +0x058: bl semTake
WRITE_UL_HPI_REG(UL_HPIA_ADDR,scraddr);
0x9ee918 +0x05c: lis r9, 0x5200 (20992)
0x9ee91c +0x060: ori r9, r9, 0x4
0x9ee920 +0x064: lwz r0, 0x20(r31)
0x9ee924 +0x068: stw r0, 0x0(r9)
for(i = 0; i < len ; i+=4)
0x9ee928 +0x06c: li r0, 0x0 (0)
0x9ee92c +0x070: stw r0, 0x18(r31)
0x9ee930 +0x074: lwz r0, 0x18(r31)
0x9ee934 +0x078: lwz r9, 0x1c(r31)
0x9ee938 +0x07c: cmpl crf1, 0, r0, r9
0x9ee93c +0x080: bc 0xc, 0x4, hpi_ul_memcpy_dsp2h + 0x88
0x9ee940 +0x084: b hpi_ul_memcpy_dsp2h + 0xbc
{
*p_cur = READ_UL_HPI_REG(UL_HPIDA_ADDR);
0x9ee944 +0x088: lwz r9, 0x14(r31)
0x9ee948 +0x08c: lis r11, 0x5200 (20992)
0x9ee94c +0x090: ori r11, r11, 0x8
0x9ee950 +0x094: lwz r0, 0x0(r11)
0x9ee954 +0x098: stw r0, 0x0(r9)
p_cur++;
0x9ee958 +0x09c: lwz r9, 0x14(r31)
0x9ee95c +0x0a0: addi r0, r9, 0x4 (4)
0x9ee960 +0x0a4: or r9, r0, r0
0x9ee964 +0x0a8: stw r9, 0x14(r31)
}
HPI_UL_UNLOCK();
0x9ee978 +0x0bc: lis r9, 0x9f (159)
0x9ee97c +0x0c0: addi r11, r9, 0x6d8 (1752)
0x9ee980 +0x0c4: lwz r3, 0x0(r11)
0x9ee984 +0x0c8: bl semGive
return;
0x9ee988 +0x0cc: b hpi_ul_memcpy_dsp2h + 0xd0
}
0x9ee98c +0x0d0: lwz r11, 0x0(r1)
0x9ee990 +0x0d4: lwz r0, 0x4(r11)
0x9ee994 +0x0d8: mtspr LR, r0
0x9ee998 +0x0dc: lwz r31, 0xfffc(r11)
0x9ee99c +0x0e0: or r1, r11, r11
0x9ee9a0 +0x0e4: blr
next prev parent reply other threads:[~2004-10-27 4:31 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-10-26 0:57 Help! soar.wu
2004-10-26 14:13 ` Help! Mark Chambers
2004-10-27 3:47 ` soar.wu [this message]
2004-10-27 3:48 ` Help! soar.wu
2004-10-27 3:49 ` Help! soar.wu
2004-10-27 12:20 ` Help! Mark Chambers
2004-10-27 13:08 ` Help! soar.wu
-- strict thread matches above, loose matches on Subject: below --
1999-06-03 1:51 Help! Jeremy Welling
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