From: Kumar Gala <galak@kernel.crashing.org>
To: linuxppc-dev@ozlabs.org
Subject: [PATCH] [POWERPC] FSL: Access PCIe LTSSM register with correct size
Date: Thu, 4 Oct 2007 00:29:59 -0500 (CDT) [thread overview]
Message-ID: <Pine.LNX.4.64.0710040029160.11519@blarg.am.freescale.net> (raw)
The LTSSM register is actual 32-bits wide so we should be doing a
dword access.
---
arch/powerpc/sysdev/fsl_pci.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
minor cleanup patch
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 98290f4..af090c9 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -160,8 +160,8 @@ static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev)
int __init fsl_pcie_check_link(struct pci_controller *hose)
{
- u16 val;
- early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
+ u32 val;
+ early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
if (val < PCIE_LTSSM_L0)
return 1;
return 0;
--
1.5.2.4
reply other threads:[~2007-10-04 5:30 UTC|newest]
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