From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 78EBDDDDF6 for ; Thu, 4 Oct 2007 15:30:30 +1000 (EST) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.13.8/8.13.8) with ESMTP id l945UPCp025447 for ; Thu, 4 Oct 2007 00:30:26 -0500 Date: Thu, 4 Oct 2007 00:29:59 -0500 (CDT) From: Kumar Gala To: linuxppc-dev@ozlabs.org Subject: [PATCH] [POWERPC] FSL: Access PCIe LTSSM register with correct size Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , The LTSSM register is actual 32-bits wide so we should be doing a dword access. --- arch/powerpc/sysdev/fsl_pci.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) minor cleanup patch diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 98290f4..af090c9 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -160,8 +160,8 @@ static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev) int __init fsl_pcie_check_link(struct pci_controller *hose) { - u16 val; - early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); + u32 val; + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); if (val < PCIE_LTSSM_L0) return 1; return 0; -- 1.5.2.4