From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from az33egw02.freescale.net (az33egw02.freescale.net [192.88.158.103]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "az33egw02.freescale.net", Issuer "Thawte Premium Server CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id F0FDDDDFC4 for ; Wed, 4 Jun 2008 07:59:24 +1000 (EST) Date: Tue, 3 Jun 2008 14:58:33 -0700 (PDT) From: Trent Piepho To: Matthew Wilcox Subject: Re: MMIO and gcc re-ordering issue In-Reply-To: <20080603213501.GD3549@parisc-linux.org> Message-ID: References: <1211852026.3286.36.camel@pasglop> <20080602072403.GA20222@flint.arm.linux.org.uk> <200806031416.18195.nickpiggin@yahoo.com.au> <20080603185541.GB3549@parisc-linux.org> <20080603213501.GD3549@parisc-linux.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Cc: linux-arch@vger.kernel.org, Nick Piggin , Russell King , linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org, scottwood@freescale.com, Linus Torvalds , David Miller , alan@lxorguk.ukuu.org.uk List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, 3 Jun 2008, Matthew Wilcox wrote: > On Tue, Jun 03, 2008 at 12:57:56PM -0700, Trent Piepho wrote: >> On Tue, 3 Jun 2008, Matthew Wilcox wrote: >>> On Tue, Jun 03, 2008 at 11:47:00AM -0700, Trent Piepho wrote: >>>> On Tue, 3 Jun 2008, Linus Torvalds wrote: >>>>> On Tue, 3 Jun 2008, Nick Piggin wrote: >>>>>> >>>>>> Linus: on x86, memory operations to wc and wc+ memory are not ordered >>>>>> with one another, or operations to other memory types (ie. load/load >>>>>> and store/store reordering is allowed). Also, as you know, store/load >>>>>> reordering is explicitly allowed as well, which covers all memory >>>>>> types. So perhaps it is not quite true to say readl/writel is strongly >>>>>> ordered by default even on x86. You would have to put in some >>>>>> mfence instructions in them to make it so. >>>> >>>> So on x86, these could be re-ordered? >>>> >>>> writel(START_OPERATION, CONTROL_REGISTER); >>>> status = readl(STATUS_REGISTER); >>> >>> You wouldn't ask for write-combining memory mapping for control or >>> status registers. >> >> But Nick said, "store/load reordering is explicitly allowed as well, which >> covers *all* memory types." > > Then Nick is confused. PCI only defines one way to flush posted writes > to a device -- doing a read from it. There's no way that reads can > be allowed to pass writes (unless you've asked for it, like with write > combining). But that requirement is for the PCI bridge, isn't it? It doesn't matter if the bridge will flush all posted writes before allowing a read if the CPU decides to give the bridge the read before the write. A powerpc CPU will certainly do this if you don't take any steps like telling it the memory is uncachable and guarded. I didn't think it was allowed on x86 (except with WC), but Nick seemed to say it was.