Re: [PATCH] POWERPC: MTD: Add cached map support to physmap_of MTD driver

[Trent Piepho <tpiepho@freescale.com>]

On Tue, 16 Dec 2008, Paul Mackerras wrote:
> Trent Piepho writes:
>> The MTD system supports operation where a direct mapped flash chip is
>> mapped twice.  The normal mapping is a standard ioremap(), which is
>> non-cached and guarded on powerpc.  The second mapping is used only for
>> reads and can be cached and non-guarded.  Currently, only the pxa2xx
>> mapping driver makes use of this feature.  This patch adds support to the
>> physmap_of driver on PPC32 platforms for this cached mapping mode.
>
> Note that having two mappings of the same physical address that differ
> in cacheability is a programming error according to the PowerPC
> architecture.
>
> Do you know that the processor implementations where you want to do
> this can cope with having two mappings with different cacheability?

Good question.  It worked for me, but I guess all powerpc32 can't handle
it.

Shame, as it provides a huge speed up.  I suppose an alternative would be
to map the chip twice at different physical addresses, by just configuring
the chip select to be twice the size it should be, and giving them
different cacheability.

Or changing the mapping for writes and then changing it back.  It wouldn't
be necessary to change the whole thing, just the page being written to.