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Tue, 5 Jan 2021 04:04:02 -0500 (EST) Date: Tue, 5 Jan 2021 10:05:28 +0100 From: Greg KH To: Santosh Sivaraj Subject: Re: [PATCH v3 5/6] mm/mmu_gather: invalidate TLB correctly on batch allocation failure and flush Message-ID: References: <20200312132740.225241-1-santosh@fossix.org> <20200312132740.225241-6-santosh@fossix.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200312132740.225241-6-santosh@fossix.org> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sasha Levin , Peter Zijlstra , stable@vger.kernel.org, "Aneesh Kumar K . V" , linuxppc-dev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Mar 12, 2020 at 06:57:39PM +0530, Santosh Sivaraj wrote: > From: Peter Zijlstra > > commit 0ed1325967ab5f7a4549a2641c6ebe115f76e228 upstream. > > Architectures for which we have hardware walkers of Linux page table > should flush TLB on mmu gather batch allocation failures and batch flush. > Some architectures like POWER supports multiple translation modes (hash > and radix) and in the case of POWER only radix translation mode needs the > above TLBI. This is because for hash translation mode kernel wants to > avoid this extra flush since there are no hardware walkers of linux page > table. With radix translation, the hardware also walks linux page table > and with that, kernel needs to make sure to TLB invalidate page walk cache > before page table pages are freed. > > More details in commit d86564a2f085 ("mm/tlb, x86/mm: Support invalidating > TLB caches for RCU_TABLE_FREE") > > The changes to sparc are to make sure we keep the old behavior since we > are now removing HAVE_RCU_TABLE_NO_INVALIDATE. The default value for > tlb_needs_table_invalidate is to always force an invalidate and sparc can > avoid the table invalidate. Hence we define tlb_needs_table_invalidate to > false for sparc architecture. > > Link: http://lkml.kernel.org/r/20200116064531.483522-3-aneesh.kumar@linux.ibm.com > Fixes: a46cc7a90fd8 ("powerpc/mm/radix: Improve TLB/PWC flushes") > Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Aneesh Kumar K.V > Cc: # 4.19 > Signed-off-by: Santosh Sivaraj > [santosh: backported to 4.19 stable] > --- > arch/Kconfig | 3 --- > arch/powerpc/Kconfig | 1 - > arch/powerpc/include/asm/tlb.h | 11 +++++++++++ > arch/sparc/Kconfig | 1 - > arch/sparc/include/asm/tlb_64.h | 9 +++++++++ > include/asm-generic/tlb.h | 15 +++++++++++++++ > mm/memory.c | 16 ++++++++-------- > 7 files changed, 43 insertions(+), 13 deletions(-) As the testing pointed out, this breaks the build on lots of arches: https://lore.kernel.org/r/CAEUSe78+F1Q9LFjpf8SQzQa6+Ak4wcPiiNcUVxEcv+KPdrYvBw@mail.gmail.com https://lore.kernel.org/r/cff87cd2-8cd5-241e-3a05-a817b1a56b8c@roeck-us.net so I'm going to drop this whole series and do a -rc2. If you still want/need this series in 4.19, please make sure it really works for everyone :) thanks, greg k-h