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Thu, 23 Feb 2023 10:47:48 -0800 (PST) Date: Thu, 23 Feb 2023 10:47:47 -0800 In-Reply-To: Mime-Version: 1.0 References: <20230217041230.2417228-1-yuzhao@google.com> <20230217041230.2417228-3-yuzhao@google.com> Message-ID: Subject: Re: [PATCH mm-unstable v1 2/5] kvm/x86: add kvm_arch_test_clear_young() From: Sean Christopherson To: Yu Zhao Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-mm@google.com, kvm@vger.kernel.org, Jonathan Corbet , Michael Larabel , x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, kvmarm@lists.linux.dev, Paolo Bonzini , Andrew Morton , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Feb 23, 2023, Yu Zhao wrote: > On Thu, Feb 23, 2023 at 11:24=E2=80=AFAM Sean Christopherson wrote: > > > > On Thu, Feb 23, 2023, Yu Zhao wrote: > > > On Thu, Feb 23, 2023 at 10:09=E2=80=AFAM Sean Christopherson wrote: > > > > > I'll take a look at that series. clear_bit() probably won't cause= any > > > > > practical damage but is technically wrong because, for example, i= t can > > > > > end up clearing the A-bit in a non-leaf PMD. (cmpxchg will just f= ail > > > > > in this case, obviously.) > > > > > > > > Eh, not really. By that argument, clearing an A-bit in a huge PTE = is also technically > > > > wrong because the target gfn may or may not have been accessed. > > > > > > Sorry, I don't understand. You mean clear_bit() on a huge PTE is > > > technically wrong? Yes, that's what I mean. (cmpxchg() on a huge PTE > > > is not.) > > > > > > > The only way for > > > > KVM to clear a A-bit in a non-leaf entry is if the entry _was_ a hu= ge PTE, but was > > > > replaced between the "is leaf" and the clear_bit(). > > > > > > I think there is a misunderstanding here. Let me be more specific: > > > 1. Clearing the A-bit in a non-leaf entry is technically wrong becaus= e > > > that's not our intention. > > > 2. When we try to clear_bit() on a leaf PMD, it can at the same time > > > become a non-leaf PMD, which causes 1) above, and therefore is > > > technically wrong. > > > 3. I don't think 2) could do any real harm, so no practically no prob= lem. > > > 4. cmpxchg() can avoid 2). > > > > > > Does this make sense? > > > > I understand what you're saying, but clearing an A-bit on a non-leaf PM= D that > > _just_ got converted from a leaf PMD is "wrong" if and only if the inte= nted > > behavior is nonsensical. >=20 > Sorry, let me rephrase: > 1. Clearing the A-bit in a non-leaf entry is technically wrong because > we didn't make sure there is the A-bit there -- the bit we are > clearing can be something else. (Yes, we know it's not, but we didn't > define this behavior, e.g., a macro to designate that bit for non-leaf > entries. Heh, by that definition, anything and everything is "technically wrong". A= n Intel CPU might support SVM, even though we know no such CPUs exist, so requiring= AMD or Hygon to enable SVM is technically wrong. > Also I didn't check the spec -- does EPT actually support the > A-bit in non-leaf entries? My guess is that NPT does.) If A/D bits are enabled, both EPT and 64-bit NPT support the Accessed bit a= t all levels irrespective of whether or not the entry maps a huge page. PAE NPT is a different story, but the TDP MMU is limited to 64-bit kernels,= i.e. requires 64-bit NPT.