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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id lt5sm2725151pjb.43.2021.11.16.08.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Nov 2021 08:07:51 -0800 (PST) Date: Tue, 16 Nov 2021 16:07:47 +0000 From: Sean Christopherson To: Paolo Bonzini Subject: Re: [PATCH 4/5] KVM: x86: Use kvm_get_vcpu() instead of open-coded access Message-ID: References: <20211105192101.3862492-1-maz@kernel.org> <20211105192101.3862492-5-maz@kernel.org> <330eb780-1963-ac1f-aaad-908346112f28@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <330eb780-1963-ac1f-aaad-908346112f28@redhat.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juergen Gross , Alexandru Elisei , Anup Patel , Janosch Frank , kvm@vger.kernel.org, Christian Borntraeger , Marc Zyngier , Huacai Chen , David Hildenbrand , linux-mips@vger.kernel.org, Nicholas Piggin , Atish Patra , Aleksandar Markovic , Paul Mackerras , James Morse , kernel-team@android.com, Claudio Imbrenda , linuxppc-dev@lists.ozlabs.org, kvmarm@lists.cs.columbia.edu, Suzuki K Poulose Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, Nov 16, 2021, Paolo Bonzini wrote: > On 11/5/21 21:03, Sean Christopherson wrote: > > But I think even that is flawed, as APICv can be dynamically deactivated and > > re-activated while the VM is running, and I don't see a path that re-updates > > the IRTE when APICv is re-activated. So I think a more conservative check is > > needed, e.g. > > > > diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c > > index 5f81ef092bd4..6cf5b2e86118 100644 > > --- a/arch/x86/kvm/vmx/posted_intr.c > > +++ b/arch/x86/kvm/vmx/posted_intr.c > > @@ -272,7 +272,7 @@ int pi_update_irte(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, > > > > if (!kvm_arch_has_assigned_device(kvm) || > > !irq_remapping_cap(IRQ_POSTING_CAP) || > > - !kvm_vcpu_apicv_active(kvm->vcpus[0])) > > + !irqchip_in_kernel(kvm) || !enable_apicv) > > return 0; > > > > idx = srcu_read_lock(&kvm->irq_srcu); > > What happens then if pi_pre_block is called and the IRTE denotes a posted > interrupt? > > I might be wrong, but it seems to me that you have to change all of the > occurrences this way. As soon as enable_apicv is set, you need to go > through the POSTED_INTR_WAKEUP_VECTOR just in case. Sorry, I didn't grok that at all. All occurences of what?