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[62.83.84.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3557a0908e4sm14132958f8f.63.2024.05.29.01.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:05:58 -0700 (PDT) From: Oscar Salvador X-Google-Original-From: Oscar Salvador Date: Wed, 29 May 2024 10:05:56 +0200 To: Christophe Leroy Subject: Re: [RFC PATCH v4 12/16] powerpc/e500: Encode hugepage size in PTE bits Message-ID: References: <10eae3c6815e3aba5f624af92321948e4684c95a.1716815901.git.christophe.leroy@csgroup.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <10eae3c6815e3aba5f624af92321948e4684c95a.1716815901.git.christophe.leroy@csgroup.eu> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Nicholas Piggin , linux-mm@kvack.org, Peter Xu , Jason Gunthorpe , Andrew Morton , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, May 27, 2024 at 03:30:10PM +0200, Christophe Leroy wrote: > Use U0-U3 bits to encode hugepage size, more exactly page shift. > > As we start using hugepages at shift 21 (2Mbytes), substract 20 > so that it fits into 4 bits. That may change in the future if > we want to use smaller hugepages. What other shifts we can have here on e500? PUD_SHIFT? Could you please spell them out here? Or even better, > > Signed-off-by: Christophe Leroy > --- > arch/powerpc/include/asm/nohash/hugetlb-e500.h | 6 ++++++ > arch/powerpc/include/asm/nohash/pte-e500.h | 3 +++ > 2 files changed, 9 insertions(+) > > diff --git a/arch/powerpc/include/asm/nohash/hugetlb-e500.h b/arch/powerpc/include/asm/nohash/hugetlb-e500.h > index 8f04ad20e040..d8e51a3f8557 100644 > --- a/arch/powerpc/include/asm/nohash/hugetlb-e500.h > +++ b/arch/powerpc/include/asm/nohash/hugetlb-e500.h > @@ -42,4 +42,10 @@ static inline int check_and_get_huge_psize(int shift) > return shift_to_mmu_psize(shift); > } > > +static inline pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags) > +{ > + return __pte(pte_val(entry) | (_PAGE_U3 * (shift - 20))); > +} > +#define arch_make_huge_pte arch_make_huge_pte > + > #endif /* _ASM_POWERPC_NOHASH_HUGETLB_E500_H */ > diff --git a/arch/powerpc/include/asm/nohash/pte-e500.h b/arch/powerpc/include/asm/nohash/pte-e500.h > index 975facc7e38e..091e4bff1fba 100644 > --- a/arch/powerpc/include/asm/nohash/pte-e500.h > +++ b/arch/powerpc/include/asm/nohash/pte-e500.h > @@ -46,6 +46,9 @@ > #define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */ > #define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */ > +#define _PAGE_HSIZE_MSK (_PAGE_U0 | _PAGE_U1 | _PAGE_U2 | _PAGE_U3) > +#define _PAGE_HSIZE_SHIFT 14 Add a comment in above explaining which P*_SHIFT we need cover with these 4bits. -- Oscar Salvador SUSE Labs