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Tue, 21 Jul 2020 06:04:02 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 002B3124052; Tue, 21 Jul 2020 06:03:59 +0000 (GMT) Received: from localhost.localdomain (unknown [9.85.85.6]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Tue, 21 Jul 2020 06:03:59 +0000 (GMT) Subject: Re: [v3 14/15] powerpc/perf: Add extended regs support for power10 platform To: Athira Rajeev , mpe@ellerman.id.au, acme@kernel.org, jolsa@kernel.org References: <1594996707-3727-1-git-send-email-atrajeev@linux.vnet.ibm.com> <1594996707-3727-15-git-send-email-atrajeev@linux.vnet.ibm.com> From: kajoljain Message-ID: Date: Tue, 21 Jul 2020 11:33:58 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <1594996707-3727-15-git-send-email-atrajeev@linux.vnet.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-21_02:2020-07-21, 2020-07-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 mlxscore=0 malwarescore=0 bulkscore=0 spamscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007210043 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, mikey@neuling.org, maddy@linux.vnet.ibm.com, kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, svaidyan@in.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 7/17/20 8:08 PM, Athira Rajeev wrote: > Include capability flag `PERF_PMU_CAP_EXTENDED_REGS` for power10 > and expose MMCR3, SIER2, SIER3 registers as part of extended regs. > Also introduce `PERF_REG_PMU_MASK_31` to define extended mask > value at runtime for power10 > > Signed-off-by: Athira Rajeev > [Fix build failure on PPC32 platform] > Suggested-by: Ryan Grimm > Reported-by: kernel test robot > --- > arch/powerpc/include/uapi/asm/perf_regs.h | 6 ++++++ > arch/powerpc/perf/perf_regs.c | 12 +++++++++++- > arch/powerpc/perf/power10-pmu.c | 6 ++++++ > 3 files changed, 23 insertions(+), 1 deletion(-) > Reviewed-by: Kajol Jain Thanks, Kajol Jain > diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h b/arch/powerpc/include/uapi/asm/perf_regs.h > index 225c64c..bdf5f10 100644 > --- a/arch/powerpc/include/uapi/asm/perf_regs.h > +++ b/arch/powerpc/include/uapi/asm/perf_regs.h > @@ -52,6 +52,9 @@ enum perf_event_powerpc_regs { > PERF_REG_POWERPC_MMCR0, > PERF_REG_POWERPC_MMCR1, > PERF_REG_POWERPC_MMCR2, > + PERF_REG_POWERPC_MMCR3, > + PERF_REG_POWERPC_SIER2, > + PERF_REG_POWERPC_SIER3, > /* Max regs without the extended regs */ > PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, > }; > @@ -60,6 +63,9 @@ enum perf_event_powerpc_regs { > > /* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */ > #define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK) > +/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */ > +#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK) > > #define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1) > +#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1) > #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ > diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c > index b0cf68f..11b90d5 100644 > --- a/arch/powerpc/perf/perf_regs.c > +++ b/arch/powerpc/perf/perf_regs.c > @@ -81,6 +81,14 @@ static u64 get_ext_regs_value(int idx) > return mfspr(SPRN_MMCR1); > case PERF_REG_POWERPC_MMCR2: > return mfspr(SPRN_MMCR2); > +#ifdef CONFIG_PPC64 > + case PERF_REG_POWERPC_MMCR3: > + return mfspr(SPRN_MMCR3); > + case PERF_REG_POWERPC_SIER2: > + return mfspr(SPRN_SIER2); > + case PERF_REG_POWERPC_SIER3: > + return mfspr(SPRN_SIER3); > +#endif > default: return 0; > } > } > @@ -89,7 +97,9 @@ u64 perf_reg_value(struct pt_regs *regs, int idx) > { > u64 PERF_REG_EXTENDED_MAX; > > - if (cpu_has_feature(CPU_FTR_ARCH_300)) > + if (cpu_has_feature(CPU_FTR_ARCH_31)) > + PERF_REG_EXTENDED_MAX = PERF_REG_MAX_ISA_31; > + else if (cpu_has_feature(CPU_FTR_ARCH_300)) > PERF_REG_EXTENDED_MAX = PERF_REG_MAX_ISA_300; > > if (idx == PERF_REG_POWERPC_SIER && > diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c > index b02aabb..f066ed9 100644 > --- a/arch/powerpc/perf/power10-pmu.c > +++ b/arch/powerpc/perf/power10-pmu.c > @@ -87,6 +87,8 @@ > #define POWER10_MMCRA_IFM3 0x00000000C0000000UL > #define POWER10_MMCRA_BHRB_MASK 0x00000000C0000000UL > > +extern u64 PERF_REG_EXTENDED_MASK; > + > /* Table of alternatives, sorted by column 0 */ > static const unsigned int power10_event_alternatives[][MAX_ALT] = { > { PM_RUN_CYC_ALT, PM_RUN_CYC }, > @@ -397,6 +399,7 @@ static void power10_config_bhrb(u64 pmu_bhrb_filter) > .cache_events = &power10_cache_events, > .attr_groups = power10_pmu_attr_groups, > .bhrb_nr = 32, > + .capabilities = PERF_PMU_CAP_EXTENDED_REGS, > }; > > int init_power10_pmu(void) > @@ -408,6 +411,9 @@ int init_power10_pmu(void) > strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10")) > return -ENODEV; > > + /* Set the PERF_REG_EXTENDED_MASK here */ > + PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31; > + > rc = register_power_pmu(&power10_pmu); > if (rc) > return rc; >